Datasheet > PPC403GB-KA28C-1

PPC403GB-KA28C-1

更新时间： 2024-11-24 23:28:59

品牌	Logo	应用领域
其他 - ETC		外围集成电路微处理器动态存储器时钟
页数	文件大小	规格书
44页	596K
描述
32-Bit Microprocessor

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数据手册

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PPC403GB-KA28C-1 数据手册

PowerPC 403GB

32-Bit RISC

Data

Sheet

Embedded Controller

Overview

Features

The PowerPC 403GB 32-bit RISC embedded

controller offers high performance and functional

integration with low power consumption. The

403GB RISC CPU executes at sustained speeds

approaching one cycle per instruction. On-chip

caches and integrated DRAM and SRAM control

functions reduce chip count and design complex-

ity in systems, while improving system through-

put.

• PowerPC RISC CPU and instruction set

architecture

• Glueless interfaces to DRAM, SRAM,

ROM, and peripherals, including byte and

half-word devices

• Separate instruction cache and write-back

data cache, both two-way set-associative

• Minimized interrupt latency

• Individually programmable on-chip control-

lers for:

External I/O devices or SRAM/DRAM memory

banks can be directly attached to the 403GB bus

interface unit (BIU). Interfaces for up to six mem-

ory banks and I/O devices, including a maximum

of two DRAM banks, can be configured individu-

ally, allowing the BIU to manage devices or

memory banks with differing control, timing, or

bus width requirements.

–Two DMA channels

–DRAM, SRAM, and ROM banks

–Peripherals

–External interrupts

• Flexible interface to external bus masters

• Hardware multiplier and divider for faster

integer arithmetic

• Thirty-two 32-bit general purpose registers

Interrupt

Controller

Timers

Applications

RISC Execution Unit

JTAG

Port

• Set-top boxes

• Consumer electronics and video games

• Telecommunications and networking

Instruction

Cache Unit

Data

Cache Unit

2-Channel

DMA

• Office automation (printers, copiers, fax

Controller

machines)

(Address

and

Control)

Specifications

• 28MHz operation

Bus Interface Unit

• Interfaces to both 3V and 5V technologies

• Low-power 3.3V operation with built-in

DRAM Controller

I/O Controller

power management and stand-by mode

• Low-cost 128 lead TQFP package

• 0.5 µm triple-level-metal CMOS

SRAM, ROM, I/O

Controls

DRAM

Controls

Data Address

Bus Bus

12 3 4 5 6 7...44

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