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PPC403GA-JC33C1 PDF预览

PPC403GA-JC33C1

更新时间: 2024-11-24 23:28:59
品牌 Logo 应用领域
其他 - ETC 外围集成电路微处理器
页数 文件大小 规格书
44页 616K
描述
32-Bit Microprocessor

PPC403GA-JC33C1 数据手册

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PowerPC 403GA  
32-Bit RISC  
Data  
Sheet  
Embedded Controller  
Overview  
Features  
The PowerPC 403GA 32-bit RISC embedded  
controller offers high performance and functional  
integration with low power consumption. The  
403GA RISC CPU executes at sustained speeds  
approaching one cycle per instruction. On-chip  
caches and integrated DRAM and SRAM control  
functions reduce chip count and design  
complexity in systems, while improving system  
throughput.  
PowerPC RISC CPU and instruction set  
architecture  
Glueless interfaces to DRAM, SRAM,  
ROM, and peripherals, including byte and  
half-word devices  
Separate instruction cache and write-back  
data cache, both two-way set-associative  
Minimized interrupt latency  
Individually programmable on-chip  
controllers for:  
External I/O devices or SRAM/DRAM memory  
banks can be directly attached to the 403GA bus  
interface unit (BIU). Interfaces for up to eight  
memory banks and I/O devices, including a  
maximum of four DRAM banks, can be  
configured individually, allowing the BIU to  
manage devices or memory banks with differing  
control, timing, or bus width requirements.  
Four DMA channels  
–DRAM, SRAM, and ROM banks  
Peripherals  
–Serial port  
–External interrupts  
Flexible interface to external bus masters  
Hardware multiplier and divider for faster  
Interrupt  
Controller  
integer arithmetic  
Timers  
Thirty-two 32-bit general purpose registers  
RISC Execution Unit  
JTAG  
Port  
Applications  
Set-top boxes  
Consumer electronics and video games  
Telecommunications and networking  
Instruction  
Cache Unit  
Data  
Cache Unit  
Serial  
Port  
4-Channel  
DMA  
Office automation (printers, copiers, fax  
On-chip  
Peripheral  
Bus  
machines)  
Controller  
Personal digital assistants (PDA)  
(Address  
and  
Control)  
Specifications  
25MHz, and 33MHz, and 40MHz versions  
Interfaces to both 3V and 5V technologies  
Bus Interface Unit  
DRAM Controller  
I/O Controller  
Low-power 3.3V operation with built-in  
power management and stand-by mode  
Low-cost 160 lead PQFP package  
0.5 µm triple-level-metal CMOS  
SRAM, ROM, I/O  
Controls  
DRAM  
Controls  
Data Address  
Bus  
Bus  

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