Datasheet > PO100HSTL23ATR

PO100HSTL23ATR

更新时间： 2025-07-18 06:04:35

品牌	Logo	应用领域
POTATO		/
页数	文件大小	规格书
6页	520K
描述
Dual Differential LVDS/LVPECL/HSTL to LVTTL Translator

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中文翻译

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技术参数
数据手册

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PO100HSTL23ATR 技术参数

生命周期：	Contact Manufacturer	包装说明：	,
Reach Compliance Code：	unknown	风险等级：	5.68
Base Number Matches：	1

PO100HSTL23ATR 数据手册

PO100HSTL23A

12/19/07

Dual Differential LVDS/LVPECL/HSTL to LVTTL Translator

FEATURES:

DESCRIPTION:

• Patented Technology

• Differential LVDS/LVPECL/HSTL to LVTTL

Translator

• Operating frequency up to 1GHz with 2pf load

• Operating frequency up to 800MHz with 5pf load

• Operating frequency up to 450MHz with 15pf load

• Very low output pin to pin skew < 150ps

• Propagation delay < 1.8ns max with 15pf load

• 2.4V to 3.6V power supply

Potato Semiconductor’s PO100HSTL23A is

designed for world top performance using

submicron CMOS technology to achieve 1GHz

LVTTL output frequency with less than 1.8ns

propagation delay.

The PO100HSTL23A is a low-skew, The small

outline 8 pin package and the low skew design to

make it ideal for applica- tions which require the

translation of a clock or a data signal.

• Industrial temperature range: –40°C to 85°C

• Available in 8-pin SOIC package

• Available in 8-pin TSSOP package

Pin Configuration

Logic Block Diagram

LVDS

LVPEC

HSTL

LVTTL

GND

Pin Description

Function

Q0, Q1

LVTTL Outputs

Differential

LVDS/LVPECL/HSTL Inputs

Positive Supply

Ground

D0, D1

GND

12 3 4 5 6

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