Switchtec PFX PCIe Gen3 Fanout Switch Family
PM8536, PM8535, PM8534, PM8533, PM8532, and PM8531
The Switchtec PFX PCIe Gen3 Fanout Switch Family comprises high-reliability
PCIe Base Specification 3.1-compliant switches supporting up to 96 lanes,
24 virtual switch partitions, 48 Non-Transparent Bridges (NTBs), hot- and
surprise-plug controllers for each port, advanced error containment, and
comprehensive diagnostics and debug capabilities.
Typical applications for the PFX include data center equipment, defense
and industrial servers, workstations, test equipment, video production and
broadcasting equipment, cellular infrastructure, access networks, metro
networks, and core networking.
Features
High-Performance Non-Blocking Switches
Highlights
• Up to 174 GB/s switching capacity
• High-reliability PCIe: robust error containment,
hot- and surprise-plug controllers per port, end-
to-end data integrity protection, ECC protection
on RAMs, high-quality, low-power SERDES
• 96-lane, 80-lane, 64-lane, 48-lane, 32-lane, and 24-lane variants
• Ports bifurcate from x2 to x16 lanes
• Up to 48 NTBs assignable to any port
• Logical Non-Transparent (NT) interconnect allows for larger topologies
(up to 256 masters)
• Comprehensive diagnostics and debugging:
PCIe generator and analyzer, per-port
performance and error counters, multiple
loopback modes, and real-time eye capture
• Supports 1+1 and N+1 failover mechanisms
• NT address translation using direct windows and multiple sub-windows
per BAR
• Significant power, cost, and board space
savings with support for:
• Supports multicast groups per port
• Up to 48 ports, 48 NTBs, and 24 virtual
switch partitions
Error Containment
• Flexible x2, x4, x8 and x16 port bifurcation
with no restrictions on configuring ports
as either upstream or downstream, or on
mapping ports to NTBs
• Advanced Error Reporting (AER) on all ports
• Downstream Port Containment (DPC) on all downstream ports
• Poisoned TLP blocking
• Completion Timeout Synthesis (CTS) to prevent an error state in an
upstream host due to incomplete non-posted transactions
• Hot- and surprise-plug controllers per port
• GPIOs configurable for different cable/connector standards
PCIe Interfaces
• Passive, managed, and optical cables
• SFF-8644, SFF-8643, SFF-8639, OCuLink, and other connectors
• SHPC-enabled slot and edge connectors
Diagnostics and Debug
• Transaction Layer Packet (TLP) generator for testing and debugging of links
and error handling
• Real-time eye capture
• Any-to-any port mirroring for debug purposes
• External loopback at PHY and TLP layers
• Errors, statistics, performance, and TLP latency counters