Datasheet > PM8353

PM8353

更新时间： 2024-09-26 22:26:27

品牌	Logo	应用领域
PMC		/
页数	文件大小	规格书
2页	102K
描述
4-Channel 1.0-1.25 Gbps Transceiver

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

PM8353 数据手册

PMC-Sierra,Inc.

PM8353 QuadPHY™

4-Channel 1.0-1.25 Gbps Transceiver

• High speed outputs which feature

requirements) which produces run length

limited data streams for serial trans-

mission.

FEATURES

• Four independent 1.0-1.25 Gbit/s

transceivers

• Four secondary channels to support

channel redundancy

• Ultra low power operation: 1.25 Watt

typical

programmable output current to

directly drive dual-terminated line

• 2.5V, 0.25 micron CMOS technology

with 3.3V tolerant I/O

• Direct interface to optical modules,

coax, or serial backplanes

A receive FIFO optionally aligns all

incoming parallel data to the local clock

domain, adding or removing IDLE

sequences as required. This simplifies

implementation of the upstream ASIC by

removing the requirement to deal with

multiple clock domains.

• Small footprint 19x19 mm, 289-pin

PBGA

• Integrated serializer/deserializer, clock

synthesis, clock recovery, and 8B/10B

encode/decode logic

APPLICATIONS

When trunking is enabled, the QuadPHY

can remove cable skew differences

equivalent to several meters, presenting

4-byte data vectors at the receive

interface exactly as they were trans-

mitted.

• Physical Coding Sublayer (PCS) logic

for Gigabit Ethernet

• Selectable 8-bit, 10-bit, or IEEE 802.3z

GMII parallel interface

• Optional Receive FIFOs which

synchronize incoming data to local

clock domain

• “Trunking” feature to de-skew and

align received parallel data across four

channels

• 100-156 MHz Single Data Rate (SDR)

parallel transmit interface with clock

forwarding

• 100-125 MHz SDR parallel receive

interface

• Extensive control of loopback, BIST,

and operating modes via 802.3

compliant MDC/MDIO serial interface

• Built-in packet generator/checker

• IEEE 1149.1 JTAG testing support

• IEEE 802.3z Gigabit Ethernet and

ANSI X3T11 Fibre Channel support

• High speed serial backplanes

• Gigabit Ethernet links

• Fibre Channel links

• Intra-system interconnect

• ASIC to PMD link

EXAMPLE ARCHITECTURE

GENERAL DESCRIPTION

The QuadPHY^TMis a Quad PHYsical

layer transceiver ideal for systems

requiring large numbers of point-to-point

gigabit links. It provides four individual

serial channels capable of operation at

up to 1.25 Gbps each, which may be

grouped together to form a single 5.0

Gbps bidirectional link. Each of the four

primary channels has a corresponding

secondary channel that can be enabled

via the MDC/MDIO serial interface.

The first figure on the next page shows

the QuadPHY in a switch application.

This implementation uses four channels

of 1.25 Gbaud per linecard, requiring

only 16 signal pins per linecard and 64

for the switch card, providing up to

16 Gbps total payload capacity to the

switch fabric.

The dotted lines in the figure depict the

system clock domains. Note that even

though the recovered clock from any or

all serial links may be asynchronous to

the local clock, the QuadPHY bridges-

these domains so that the switch fabric

and linecards may be designed in only a

single clock domain.

The QuadPHY includes 8B/10B block

coding logic (compliant with 802.3z

Gigabit Ethernet and Fibre Channel

BLOCK DIAGRAM

Transmit Channel A (1 of 4)

Parallel

Data In

FIFO

Serial

Transmit

Data

TX Byte

Clock

8B/10B

Encoder

Serializer

PCS

Receive Channel A (1 of 4)

Parallel

Data Out

Clock

Recovery

10B/8B

Decoder

Deserialize &

Byte Align

FIFO

PCS

Serial

Receive

Data

RX Byte

Clock

REFCLK

Common Control Logic

Clock Synthesizer

MDC/MDIO

Serial

Management

Static Controls

PLL LOCK

PMC-2000673 (R3)

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE

中文翻译

下载PDF

与PM8353相关器件

型号	品牌	获取价格	描述	数据表
PM8354A-NGI	MICROSEMI	获取价格	Interface Circuit, 4-Trnsvr, CMOS, PBGA289, 19 X 19 MM, 1.76 MM HEIGHT, ROHS COMPLIANT, MO
PM8354A-NI	MICROSEMI	获取价格	Interface Circuit, 4-Trnsvr, CMOS, PBGA289, 19 X 19 MM, 1.76 MM HEIGHT, MO-205BD, CABGA-28
PM8354-NGI	MICROSEMI	获取价格	Interface Circuit, 4-Trnsvr, CMOS, PBGA289, 19 X 19 MM, 1.76 MM HEIGHT, ROHS COMPLIANT, MO
PM8354-NI	MICROSEMI	获取价格	Interface Circuit, 4-Trnsvr, CMOS, PBGA289, 19 X 19 MM, 1.76 MM HEIGHT, MO-205BD, CABGA-28
PM8355	PMC	获取价格	4-Channel 2.125, 2.5 and 3.125 Gbit/s Transceiver with Half-rate Support
PM8355?	ETC	获取价格	Short Form PMC-2000791 PM8355 QuadPHY-II 4-Channel 2.125\| 2.5 to 3.125 Gbit/s Transceiver
PM8355-NI	PMC	获取价格	Ethernet Transceiver, 4-Trnsvr, CMOS, PBGA289,
PM8357	MICROSEMI	获取价格	Interface Circuit, 4-Trnsvr, CMOS, PBGA196, 15 X 15 MM, 1.40 MM HEIGHT, CABGA-196
PM8357-NI-P	PMC	获取价格	Telecom IC,
PM8358-NGI	PMC	获取价格	Interface Circuit, 4-Trnsvr, CMOS, PBGA289, 19 X 19 MM, 1.76 MM HEIGHT, 1 MM PITCH, MO-205

与PM8353相关文章

塔塔电子与力积电达成技术转让协议，携手建设印度首座晶圆厂
2024-09-29

16
英特尔震撼发布：128核心256线程的至强6性能核处理器
2024-09-29

13
SK海力士量产12层HBM3E，容量高达36GB
2024-09-27

17
意法半导体传感器驱动Sphere，开启沉浸式电影新时代
2024-09-27

26

产品中心

服务支持

精选活动

关于我们

帮助中心

PM8353

PM8353 数据手册

与PM8353相关器件

与PM8353相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

PM8353

PM8353 数据手册

与PM8353相关器件

与PM8353相关文章

您还可以找

您在本页遇到什么问题？