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PM8313 PDF预览

PM8313

更新时间: 2024-11-01 22:26:27
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2页 50K
描述
M13 Multiplexer/Demultiplexer

PM8313 数据手册

 浏览型号PM8313的Datasheet PDF文件第2页 
PM8313  
D3MX  
PMC-Sierra,Inc.  
M13 Multiplexer/Demultiplexer  
Provides a generic 8-bit  
M23 AND M12 MULTIPLEX/  
DEMULTIPLEX SECTIONS  
FEATURES  
• Integrates a complete M13 multiplexer/  
demultiplexer in a single monolithic  
device.  
• Integral framer supports the M23 or C-  
bit parity DS3 format with path  
maintenance datalink processing and  
bit-oriented code support for Far-End  
Alarm and Control (FEAC) channel  
termination.  
• Supports either the M12 or the G.747  
formats to allow DS1 or E1 signals to  
be multiplexed into a DS3 signal.  
• Allows the M12 stages to be bypassed  
allowing direct input of DS2 signals.  
• Generates an interrupt upon detection  
of various alarms, events, or changes  
in status. Identification of interrupt  
sources, masking of interrupt sources,  
and acknowledgement of interrupts is  
provided via internal registers.  
• Application-compatible with the  
PM4351 COMET T1 Transceiver,  
PM4341A T1XC T1 Transceiver,  
PM4344 TQUAD Quad T1 Framer,  
PM4388 TOCTL Octal T1 Framer,  
PM6341 E1XC E1 Transceiver,  
PM6344 EQUAD Quad E1 Framer,  
PM6388 EOCTL Octal E1 Framer,  
PM4314 QDSX Quad E1/T1 LIU, and  
the PM7344 S/UNI®-MPH.  
microprocessor interface for  
configuration, control, and status  
monitoring.  
Low power 5 V CMOS technology.  
Available in a high density (28 by  
28 mm) 208-pin Plastic Quad Flat  
Pack (PQFP) package.  
Supports combination of four DS1 bit  
streams or the combination of three E1  
bit streams per G.747 into a single  
M12 stream.  
Supports per-DS2 payload loopback  
requests via C-bits or microprocessor  
control.  
Accumulates DS2 M-bit, F-bit, and  
G.747 framing bit/word error events.  
Supports DS2 AIS assertion based on  
DS3 LOF, or under microprocessor  
control.  
Supports DS2 tributary AIS activation/  
deactivation in either direction under  
microprocessor control.  
DS3 FRAMER SECTION  
Detects/inserts DS3 Alarm Indication  
Signal (AIS) and Idle signal - operates  
correctly in the presence of 10-3 Bit  
Error Ratio (BER).  
Extracts/inserts the X,P,M,F,C and the  
stuff opportunity bits and serializes for  
optional external processing.  
Extracts/inserts the C-bit parity mode  
path maintenance datalink and  
serializes for optional external  
Inserts/detects per-DS1 payload  
loopback requests transmitted via  
C-bits.  
processing.  
Extracts/inserts the C-bit parity bit-  
oriented codes in the FEAC channel.  
Detects and accumulates EXcessive  
Zeros (EXZ), Loss Of Signal (LOS),  
Line Code Violations (LCVs) P-bit,  
F-bit, or M-bit errors, C-bit parity errors  
and Far-End Block Errors (FEBEs).  
Supports DS3 line loopback and DS3  
diagnostic loopback modes to assist in  
fault isolation.  
APPLICATIONS  
M23 or C-Bit Parity Format DS1 to  
DS3 Mux/Demux Equipment  
Fractional T3 Access Equipment  
DS2-to-DS3 Mux/Demux Equipment  
DS1-to-DS3 Mux/Demux Equipment  
Supporting G.747 Tributary Format  
BLOCK DIAGRAM  
#1  
Tx  
XBOC  
Transmit  
FEAC  
XFDL  
Transmit  
HDLC  
TD1CLK4  
TD1DAT4  
O/H  
Access  
RD1DAT[3:1]  
MX12  
RD1CLK[3:1]  
M12  
MUX/  
DEMUX  
TCLK  
TPOS/TDAT  
TNEG/TMFP  
RD1CLK[3:1]  
RD1DAT[3:1]  
TRAN  
DS3 Transmit  
Framer  
B3ZS  
Decode  
DS2  
FRMR  
Framer  
MX23  
M23  
MUX/DEMUX  
RD1CLK4  
RD1DAT4  
FRMR  
DS3 Receive  
Framer  
RCLK/VCLK  
RPOS/RDAT  
RNEG/RLCV  
B3ZS  
Decode  
One of seven M12  
Remaining Six M12  
TD1CLK[28:5]  
TD1DAT[28:5]  
RD1CLK[28:5]  
RD1DAT[28:5]  
PMON  
Perfor-  
mance  
#2 - #7  
RBOC  
Receive  
FEAC  
RFDL  
Receive  
HDLC  
Rx  
O/H  
Access  
MPIF  
Microprocessor  
Interface  
Monitor  
Counters  
PMC-920522 (R10)  
© 1998 PMC-Sierra, Inc. October, 1998  

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