Datasheet > PM7800

PM7800

更新时间： 2024-01-11 19:18:33

品牌	Logo	应用领域
PMC		/
页数	文件大小	规格书
2页	29K
描述
Digital Correction Signal Processor

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数据手册

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PM7800 数据手册

PM7800

PALADIN-10

Preliminary

Digital Correction Signal Processor

• 48 general-purpose IO pins, eight of

which are edge-triggered interrupt

sources.

• Standard five-signal IEEE 1149.1

JTAG test port for boundary scan

board test purposes.

FEATURES

APPLICATIONS

• Digitial Adaptive Pre-Distortion for

wideband linearization of power

amplifiers in wireless basestations.

• Digitial Correction for Analog

Quadrature Modulation Distortion.

• Digital Soft Pre-compression for

efficiency management.

• Multi-carrier WCDMA Base

Transceiver Subsystems (BTS).

• CDMA2000 BTS (requires firmware

upgrade).

• GSM/TDMA/EDGE BTS (requires

firmware upgrade).

PACKAGING

• Input Signal Bandwidth up to 10 MHz.

Sample rate up to 80 MHz.

• Programmable, variable input data

rate.

• 16-bit microprocessor bus interface for

adaptive control processor

compensation engine.

• Low-power 1.8 V CMOS core logic

with 3.3 V CMOS/TTL compatible

digital inputs and digital outputs.

• Industrial temperature range (-40 °C to

+85 °C).

• 304-pin SBGA with a body size of

31mm x 31mm.

• Serial interface (configurable to SPI or

I2C operation) for update of power and

carrier values.

BLOCK DIAGRAM

PALADIN-10 Padring

PALADIN-10

JTAG

DCLK

REFCLK

CPUCLK

PALADIN-10 Core

RESET_N

VREF

Pre-

Predistorter

Circuitry

Predistortion

Filter

Modulation

Circuitry

Input Module

SCS_N

SCLK

HOP_N

CPU

Interface

Capture

Module

GPIO

VOBS

PMC-2001613 (P1)

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE

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