Datasheet > 电信电路 > ATM/SONET/SDH 集成电路> PM7350-BI

PM7350-BI

更新时间： 2024-11-12 12:59:31

品牌	Logo	应用领域
PMC		复用器
页数	文件大小	规格书
2页	37K
描述
Support Circuit, 1-Func, CMOS, PBGA160, 15 X 15 MM, 1.61 MM HEIGHT, PLASTIC, BGA-160

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技术参数
数据手册

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PM7350-BI 技术参数

是否Rohs认证：	不符合	生命周期：	Transferred
包装说明：	15 X 15 MM, 1.61 MM HEIGHT, PLASTIC, BGA-160	Reach Compliance Code：	compliant
风险等级：	5.86	应用程序：	ATM
JESD-30 代码：	S-PBGA-B160	JESD-609代码：	e0
长度：	15 mm	湿度敏感等级：	3
功能数量：	1	端子数量：	160
最高工作温度：	85 °C	最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY	封装代码：	BGA
封装等效代码：	BGA160,14X14,40	封装形状：	SQUARE
封装形式：	GRID ARRAY	峰值回流温度（摄氏度）：	225
电源：	3.3 V	认证状态：	Not Qualified
座面最大高度：	1.8 mm	子类别：	ATM/SONET/SDH ICs
最大压摆率：	0.3 mA	标称供电电压：	3.3 V
表面贴装：	YES	技术：	CMOS
电信集成电路类型：	ATM/SONET/SDH SUPPORT CIRCUIT	温度等级：	INDUSTRIAL
端子面层：	Tin/Lead (Sn/Pb)	端子形式：	BALL
端子节距：	1 mm	端子位置：	BOTTOM
处于峰值回流温度下的最长时间：	30	宽度：	15 mm
Base Number Matches：	1

PM7350-BI 数据手册

PM7350

S/UNI-DUPLEX

PMC-Sierra,Inc.

Dual Serial Link, PHY Multiplexer

• 160 ball PBGA, 15mm x 15mm.

• 8/16 bit, 52 MHz extended UTOPIA L2

bus slave (compatible with PM7351

S/UNI-VORTEX).

• 16 port, 4 pin clocked serial data

interface (Tx & Rx), with integrated

I.432 ATM cell delineation.

FEATURES

• In the LVDS receive direction: selects

traffic from the LVDS link marked

active and demultiplexes the individual

cell streams to the appropriate PHY

device.

• In the LVDS transmit direction: accepts

52-56 byte cell streams from up to 32

UTOPIA L2 compatible PHY devices,

multiplexing into a single cell stream

carried over two high speed LVDS

serial interfaces.

• Cell read/write to both LVDS links

available through the processor port.

Provides optional hardware assisted

CRC32 calculation across cells to

support an embedded inter-processor

communication channel across the

LVDS links.

• Integrated analog/digital device that

interfaces a UTOPIA L2 bus to a serial

backplane with optional 1:1 protection

using high speed Low Voltage

Differential Signal (LVDS) serial links.

• For framers or modems without

UTOPIA bus interfaces: optionally

provides cell delineation (I.432) across

16 clock and data (bit serial)

LVDS INTERFACES

• Dual 4 wire LVDS serial transceivers

each operating at up to 200 Mb/s.

• Operates across PCB or backplane

traces, or across up to 10 meters of 4

wire twisted pair cabling for inter-shelf

communications.

• Fully integrated LVDS clock synthesis

and recovery. No external analog

components are required.

interfaces.

• Interworks with PM7351

S/UNI-VORTEX devices to implement

a point-to-multipoint serial backplane

architecture, with optional 1:1

protection of the common card.

• Interfaces to another S/UNI-DUPLEX

device (via a single LVDS link) to

create a simple point-to-point “UTOPIA

bus extension” capability.

• Usable bandwidth (excludes system

overhead) of 186 Mb/s.

LVDS TRANSMIT DIRECTION

PHY/FRAMER INTERFACES

• Interfaces to two S/UNI-DUPLEX

devices to create a 1:1 protected bus

extension.

• Requires no external memory devices.

• Low power 3.3V CMOS technology.

• Standard 5 pin P1149 JTAG port.

• Simple round-robin multiplex of up to

32 PHYs (or 16 clock/data interfaces)

plus the microprocessor port’s cell

transfer buffer.

• Multiplexed cell stream broadcast to

both LVDS simultaneously.

One of three modes can be selected:

• 8/16 bit, 33 MHz UTOPIA L2 bus

master (also supports expanded length

cells).

BLOCK DIAGRAM

IBUS8

IANYPHY

IMASTER

IENB

SCI-PHY

Receive

Master/

Transmit

Slave

IADDR[4:0]

IAVALID

IDAT[15:0]

IPRTY

ISOC

Per-PHY

Buffers

TXD1+

TXD1-

RXD1+

ISX

IFCLK

ICA

RXD1-

Cell Processor

TXD2+

LRXD[15:0]

LRXC[15:0]

TXD2-

Time-Sliced ATM

Elastic Store

Transmission

Convergence

Per-PHY

Buffers

RXD2+

LTXD[15:0]

LTXC[15:0]

RXD2-

OBUS8

OANYPHY

OMASTER

OENB

OADDR[4:0]

OAVALID

ODAT[15:0]

OPRTY

OSOC

SCI-PHY

Transmit

Master/

Receive Slave

Clock

Synthesis

JTAG Test Access

Port

OSX

OFCLK

OCA

Microprocessor Interface

SCIANY

PMC-990147 (P2)

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE

1999 PMC-Sierra, Inc.

中文翻译

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与PM7350-BI相关器件

型号	品牌	获取价格	描述	数据表
PM7350-PGI	PMC	获取价格	Support Circuit, 1-Func, CMOS, PBGA160, 15 X 15 MM, 1.81 MM HEIGHT, PLASTIC, BGA-160
PM7350-PI	PMC	获取价格	DUAL SERIAL LINK PHY MULTIPLEXER
PM7351	PMC	获取价格	OCTAL SERIAL LINK MULTIPLEXER
PM7351-BGI	PMC	获取价格	Support Circuit, 1-Func, CMOS, PBGA304, 31 X 31 MM, 1.51 MM HEIGHT, 1.27 MM PITCH, SBGA-30
PM7351-BI	PMC	获取价格	OCTAL SERIAL LINK MULTIPLEXER
PM73-560K-RC	BOURNS	获取价格	General Purpose Inductor, 56uH, 10%, 1 Element, Ferrite-Core, SMD, ROHS COMPLIANT
PM7364	PMC	获取价格	Frame Engine and Datalink Manager
PM7364-BGI	MICROSEMI	获取价格	Multi Protocol Controller, CMOS, PBGA256,
PM7364-BI	PMC	获取价格	FRAME ENGINE AND DATA LINK MANAGER
PM7364-BI	MICROSEMI	获取价格	Multi Protocol Controller, CMOS, PBGA256,

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