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PM7350 PDF预览

PM7350

更新时间: 2024-09-23 22:21:59
品牌 Logo 应用领域
PMC 复用器
页数 文件大小 规格书
2页 37K
描述
Dual Serial Link, PHY Multiplexer

PM7350 数据手册

 浏览型号PM7350的Datasheet PDF文件第2页 
PM7350  
S/UNI-DUPLEX  
PMC-Sierra,Inc.  
Dual Serial Link, PHY Multiplexer  
• 160 ball PBGA, 15mm x 15mm.  
• 8/16 bit, 52 MHz extended UTOPIA L2  
bus slave (compatible with PM7351  
S/UNI-VORTEX).  
• 16 port, 4 pin clocked serial data  
interface (Tx & Rx), with integrated  
I.432 ATM cell delineation.  
FEATURES  
• In the LVDS receive direction: selects  
traffic from the LVDS link marked  
active and demultiplexes the individual  
cell streams to the appropriate PHY  
device.  
• In the LVDS transmit direction: accepts  
52-56 byte cell streams from up to 32  
UTOPIA L2 compatible PHY devices,  
multiplexing into a single cell stream  
carried over two high speed LVDS  
serial interfaces.  
• Cell read/write to both LVDS links  
available through the processor port.  
Provides optional hardware assisted  
CRC32 calculation across cells to  
support an embedded inter-processor  
communication channel across the  
LVDS links.  
• Integrated analog/digital device that  
interfaces a UTOPIA L2 bus to a serial  
backplane with optional 1:1 protection  
using high speed Low Voltage  
Differential Signal (LVDS) serial links.  
• For framers or modems without  
UTOPIA bus interfaces: optionally  
provides cell delineation (I.432) across  
16 clock and data (bit serial)  
LVDS INTERFACES  
• Dual 4 wire LVDS serial transceivers  
each operating at up to 200 Mb/s.  
• Operates across PCB or backplane  
traces, or across up to 10 meters of 4  
wire twisted pair cabling for inter-shelf  
communications.  
• Fully integrated LVDS clock synthesis  
and recovery. No external analog  
components are required.  
interfaces.  
• Interworks with PM7351  
S/UNI-VORTEX devices to implement  
a point-to-multipoint serial backplane  
architecture, with optional 1:1  
protection of the common card.  
• Interfaces to another S/UNI-DUPLEX  
device (via a single LVDS link) to  
create a simple point-to-point “UTOPIA  
bus extension” capability.  
• Usable bandwidth (excludes system  
overhead) of 186 Mb/s.  
LVDS TRANSMIT DIRECTION  
PHY/FRAMER INTERFACES  
• Interfaces to two S/UNI-DUPLEX  
devices to create a 1:1 protected bus  
extension.  
• Requires no external memory devices.  
• Low power 3.3V CMOS technology.  
• Standard 5 pin P1149 JTAG port.  
• Simple round-robin multiplex of up to  
32 PHYs (or 16 clock/data interfaces)  
plus the microprocessor port’s cell  
transfer buffer.  
• Multiplexed cell stream broadcast to  
both LVDS simultaneously.  
One of three modes can be selected:  
• 8/16 bit, 33 MHz UTOPIA L2 bus  
master (also supports expanded length  
cells).  
BLOCK DIAGRAM  
IBUS8  
IANYPHY  
IMASTER  
IENB  
SCI-PHY  
Receive  
Master/  
Transmit  
Slave  
IADDR[4:0]  
IAVALID  
IDAT[15:0]  
IPRTY  
ISOC  
Per-PHY  
Buffers  
TXD1+  
TXD1-  
RXD1+  
ISX  
IFCLK  
ICA  
RXD1-  
Cell Processor  
TXD2+  
LRXD[15:0]  
LRXC[15:0]  
TXD2-  
Time-Sliced ATM  
Elastic Store  
Transmission  
Convergence  
Per-PHY  
Buffers  
RXD2+  
LTXD[15:0]  
LTXC[15:0]  
RXD2-  
OBUS8  
OANYPHY  
OMASTER  
OENB  
OADDR[4:0]  
OAVALID  
ODAT[15:0]  
OPRTY  
OSOC  
SCI-PHY  
Transmit  
Master/  
Receive Slave  
Clock  
Synthesis  
JTAG Test Access  
Port  
OSX  
OFCLK  
OCA  
Microprocessor Interface  
SCIANY  
PMC-990147 (P2)  
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE  
1999 PMC-Sierra, Inc.  

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