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PM7334 PDF预览

PM7334

更新时间: 2024-11-12 21:21:59
品牌 Logo 应用领域
PMC /
页数 文件大小 规格书
2页 752K
描述
Telecom IC,

PM7334 技术参数

生命周期:TransferredReach Compliance Code:unknown
风险等级:5.7Base Number Matches:1

PM7334 数据手册

 浏览型号PM7334的Datasheet PDF文件第2页 
PM7334 S/UNI-MPH  
Quad T1/E1 Multi-PHY SATURN User Network Interface  
Released Product Brief  
Supports line and path performance monitoring according to ANSI  
specifications. Accumulators are provided for counting ESF CRC-6  
errors, framing bit errors, LCVs, and LOF, or frame alignment events.  
FEATURES  
Monolithic single-chip quad ATM Physical Layer User Network  
Interface (UNI) operating at 1.544 Mbit/s or 2.048 Mbit/s.  
Provides ESF bit-oriented code detection/generation, and an HDLC  
Integrates a quad full-featured dualmode T1/E1 framer/transmitter  
for terminating four duplex 1.544 Mbit/s DS1 or four duplex 2.048  
Mbit/s E1 signals. Recovers T1/E1 clock and data using a digital  
phase locked loop  
interface for terminating/generating the ESF datalink.  
Extracts/inserts the datalink in ESF mode.  
E1 FRAMER/TRANSMITTER  
Supports G.704 2048 kbit/s format using HDB3 or AMI line coding.  
Implements the ATM Forum UNI Specification V3.1 for DS1 and E1  
transmission rates.  
Supports CRC multiframe alignment or the signalling multiframe  
Implements the ATM physical layer for Broadband ISDN according  
alignment.  
to ITU-T Recommendation I.432.  
Declares red and AIS alarms using Q.516 recommended integration  
periods. Provides LOS detection, and indicates loss of frame  
alignment (OOF), loss of signalling, and loss of CRC multiframe  
alignment.  
Implements direct mapping into four T1 or E1 streams according to  
ITU-T Recommendation G.804.  
Provides UTOPIA L1-compliant, UTOPIA L2-compatible ATM-PHY  
interface with parity and multi-PHY control signals.  
Supports line and path performance monitoring according to ITU-T  
recommendations. Accumulators are provided for counting CRC-4  
errors, FEBE, frame sync errors, and LCVs.  
Software-compatible with the PM4341A T1XC, PM6341 E1XC,  
PM4351 COMET, PM5346 S/UNI®- LITE and PM7345 S/UNI-PDH.  
Supports reception and transmission of remote alarm and AIS.  
Provides an HDLC interface for terminating/generating a datalink.  
Application-compatible with the PM8313 D3MX, PM4314 QDSX, and  
PM7323 RCMP-200.  
Provides a generic 8-bit microprocessor bus interface for  
Supports the timeslot 16 (64 kbit/s) datalink which may be used for  
configuration, control, and status monitoring.  
common channel signalling, or any combination of the national bits.  
Low power, +5 V, CMOS technology.  
Packaged in 128-pin rectangular (14 mm by 20 mm) PQFP package.  
APPLICATIONS  
ATM Switches Supporting DS1 or E1 UNI Ports  
T1 FRAMER/TRANSMITTER  
Supports SF or ESF format signals using B8ZS or AMI line code.  
ATM Switches Supporting DS3 or E3 Ports Carrying Multiplexed DS1  
Provides Loss Of Signal (LOS) detection and red, yellow and Alarm  
Indication Signal (AIS) alarm detection. Supports transmission of  
(AIS) or yellow alarm signal in all formats.  
or E1 UNI Signals  
ATM Switches Supporting SONET/SDH Ports Carrying Tributary  
Mapped DS1 or E1 UNI Signals  
Detects violations of the ANSI T1.403 12.5% pulse density rule over  
a moving 192-bit window.  
ATM Customer Premise Equipment Supporting Multiple DS1 or E1  
UNI Ports  
Block Diagram  
TSOC  
TDAT[7:0]  
Bit-oriented  
HDLC  
JTAG Test Access Port  
TXPRTY  
Code  
Transmitter  
TCA[4:1]  
Transmitter  
TWRENB[4]/TCAMPH  
TWRENB[3]/TWA[1]  
TWRENB[2]/TWA[0]  
TWRENB[1]/TWRMPHB  
In-band  
Loopback  
Code  
TCLK0[4:1]  
Digital  
Transport  
Interface  
Pulse  
Density  
Enforcer  
Transmit  
ATM Cell  
Processor  
Transmit  
ATM 4-Cell  
FIFO  
TDP/TDD[4:1]  
T1/E1 Framing Insertion  
TDN/TOHO[4:1]  
Generator  
Multi-PHY  
Interface  
TFCLK  
RSOC  
RDAT[7:0]  
RCLKI[4:1]  
RDP/RDD[4:1]  
Digital  
Receive  
Interface  
Receive  
ATM Cell  
Processor  
Receive  
ATM 4-Cell  
FIFO  
RXPRTY  
T1/E1 Framer  
RCA[4:1]  
RDN/RLCV/ROH[4:1]  
RRDENB[4]/RCAMPH  
RRDENB[3]/RRA[1]  
RRDENB[2]/RRA[0]  
RRDENB[1]/RRDMPHB  
RFCLK  
Pulse  
Density  
Violation Receiver  
Detector  
Bit-oriented  
Code  
Receiver  
In-band  
Code  
Detector  
HDLC  
Performance  
Monitor  
Alarms  
Integrator  
Microprocessor Interface  
PMC-941028, Issue 5  
Copyright © 2012 PMC-Sierra, Inc.  
All rights reserved. Proprietary and Confidential to PMC-Sierra and for its customers’ internal use.  

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