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PM5390

更新时间： 2024-01-26 19:52:17
品牌 Logo 应用领域
PMC 异步传输模式以太网ATM
页数 文件大小 规格书
2页 47K
描述
10 Gbit/s Physical Layer Device for POS, ATM and Ethernet

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中文翻译

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PM5390 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
包装说明：35 X 35 MM, 3.04 MM HEIGHT, MS-034AAR-1, FCBGA-1152Reach Compliance Code：compliant
风险等级：5.86应用程序：ATM;SDH;SONET
JESD-30 代码：S-PBGA-B1152JESD-609代码：e0
长度：35 mm湿度敏感等级：4
功能数量：1端子数量：1152
最高工作温度：105 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：BGA
封装等效代码：BGA1152,34X34,40封装形状：SQUARE
封装形式：GRID ARRAY峰值回流温度（摄氏度）：225
电源：1.8,3.3 V认证状态：Not Qualified
座面最大高度：3.32 mm子类别：ATM/SONET/SDH ICs
标称供电电压：1.8 V表面贴装：YES
技术：CMOS电信集成电路类型：ATM/SONET/SDH NETWORK INTERFACE
温度等级：INDUSTRIAL端子面层：TIN LEAD
端子形式：BALL端子节距：1 mm
端子位置：BOTTOM处于峰值回流温度下的最长时间：30
宽度：35 mmBase Number Matches：1

PM5390 数据手册

 浏览型号PM5390的Datasheet PDF文件第2页 
PM5390  
S/UNI®-9953  
Advance  
10 Gbit/s Physical Layer Device for POS, ATM and Ethernet  
•
•
4 x STS-48c (4 x STM-16-16c).  
POS/ATM  
GENERAL DESCRIPTION  
STS-192 (STM-64) channelized  
down to STS-48c (STM-16c).  
• Implements the ATM Forum User  
Network Interface Specification and  
the ATM physical layer for Broadband  
ISDN according to CCITT Rec. I.432.  
• Implements the Point-to-Point Protocol  
(PPP) over SONET/SDH specification  
according to RFC 2615(1619)/1662 of  
the PPP Working Group of the Internet  
Engineering Task Force (IETF).  
• The S/UNI-9953 is a single chip ATM,  
POS and 10 Gigabit Ethernet User-  
Network Interface operating at 9953.28  
Mbit/s and 10.3 Gbit/s. The S/UNI  
9953 is intended for use in OC-192c  
and high-density OC-48c POS/ATM  
applications as well as 10 Gigabit  
Ethernet WAN and LAN PHY port  
cards.  
• Supports alarm signal  
insertion/detection, B1/2/3 processing  
and insertion/termination of SONET  
Section/Line/Path overhead bytes (or  
SDH equivalents).  
• Provides ATM and POS payload  
processing for:  
•
•
•
STS-192c (STM-64-64c)  
10 GIGABIT ETHERNET  
4 x STS-48c (4 x STM-16-16c).  
• Implements 10 Gigabit Ethernet WAN  
and LAN PHY according the IEEE  
P802.3ae standard currently under  
development.  
• Provides standard IEEE P802.3ae 10  
Gigabit Ethernet Media Access  
Controller (10GMAC) for frame  
verification.  
FEATURES  
STS-192 (STM-64) channelized  
down to STS-48c (STM-16c).  
• Provides WAN Interface Sub-layer  
(WIS), Physical Coding Sub-layer  
(PCS), and Media Access Controller  
(MAC) functionality for OC-192c rate  
10 Gigabit Ethernet WAN PHY  
datastream.  
• Provides PCS and MAC layer  
functionality for 10.3 Gbit/s 10 Gigabit  
Ethernet LAN PHY datastream.  
• Supports framing, scrambling/  
descrambling and pointer processing  
for the following:  
INTERFACES  
• Provides SATURN® POS-PHY™  
Level 4 16-bit LVDS System-side  
Interface (clocked at 700 MHz  
nominal).  
• Directly connects to optics via 16 bit by  
622 MHz OIF SFI-4 (OIF99.102) or 16  
bit by 622/645 MHz IEEE P802.3ae  
XSBI line-side interfaces.  
• Implements IEEE P802.3ae 64B/66B  
Physical Coding Sub-layer (PCS).  
10 GIGABIT ETHERNET MAC  
• Verifies frame integrity (FCS and  
length checks).  
•
STS-192c (STM-64-64c).  
BLOCK DIAGRAM  
Rx SONET  
LVDS I/F  
BER  
Monitor  
APS  
Rx  
Transport  
O/H  
RSTAT  
RSCLK  
Rx Path  
O/H  
Processor  
Rx 64B/  
66B  
Decoder  
Rx Payload  
Aligner  
10 Gigabit  
Ethernet  
MAC  
XSBI/  
SFI-4  
Processor  
Ingress POS-PHY  
Flexible Level 4  
Rx  
Interface  
RXDATA+/-  
RXCLK+/-  
RCTL+/-  
RDAT+/-  
FIFO  
Interface  
RDCLK +/-  
Rx Cell/  
Frame  
Processor  
PL4 REF +/-  
Tx  
Transport  
O/H  
Tx High-  
Order Path  
O/H  
TDCLK +/-  
TDAT+/-  
TCTL+/-  
Tx 64B/66B  
Encoder  
10 Gigabit  
Ethernet  
MAC  
XSBI/  
SFI-4  
Tx  
Processor  
Processor  
Egress POS-PHY  
Flexible Level 4  
TXCLK+/-  
TXDATA +/-  
Interface  
FIFO  
Interface  
TXCLK_SRC+/-  
Tx Cell/  
Frame  
Processor  
TSTAT  
TSCLK  
APS  
Microprocessor  
JTAG  
LVDS I/F  
PMC-2000181 (A2)  
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE  
Copyright PMC-Sierra, Inc. 2001  
12

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