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PM5384-NGI PDF预览

PM5384-NGI

更新时间： 2024-01-15 07:22:04
品牌 Logo 应用领域
PMC 异步传输模式ATM
页数 文件大小 规格书
2页 33K
描述
ATM/SONET/SDH IC, CMOS, PBGA196,

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中文翻译

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PM5384-NGI 技术参数

是否Rohs认证： 不符合生命周期：Transferred
包装说明：BGA, BGA196,14X14,40Reach Compliance Code：compliant
风险等级：5.86JESD-30 代码：S-PBGA-B196
湿度敏感等级：3端子数量：196
最高工作温度：85 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：BGA
封装等效代码：BGA196,14X14,40封装形状：SQUARE
封装形式：GRID ARRAY电源：2.5,3.3 V
认证状态：Not Qualified子类别：ATM/SONET/SDH ICs
最大压摆率：119 mA表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子形式：BALL端子节距：1 mm
端子位置：BOTTOMBase Number Matches：1

PM5384-NGI 数据手册

 浏览型号PM5384-NGI的Datasheet PDF文件第2页 
PM5384  
S/UNI®-1x155  
Advance  
Single Channel OC-3c ATM and POS Physical Layer Device  
• Provides a UTOPIA Level 2, 8-bit wide  
system interface (clocked up to 52  
MHz) with parity support for ATM  
applications.  
• Provides a UTOPIA Level 2, 16-bit  
wide system interface (clocked up to  
52 MHz) with parity support for ATM  
applications.  
• Provides a SATURN POS-PHY Level  
2, 16-bit system interface (clocked up  
to 52 MHz) for Packet over  
SONET/SDH (POS) applications  
(similar to UTOPIA Level 2, but  
adapted for packet transfer).  
• Provides support functions for 1+1  
APS operation.  
• Low power 2.5/3.3 V CMOS with 5 V  
FEATURES  
• Single chip ATM and Packet over  
SONET/SDH Physical Layer Device  
operating at 155.52 Mbit/s.  
• Implements the ATM Forum User  
Network Interface (UNI) and the ATM  
physical layer for Broadband ISDN  
according to CCITT Recommendation  
I.432.  
• Implements Point-to-Point Protocol  
(PPP) over SONET/SDH according to  
RFC 2615.  
TTL-compatible digital inputs/outputs  
(PECL inputs/outputs are 3.3 V and  
5 V compatible).  
• Industrial temperature range (-40°C to  
+85°C).  
• 15 mm x15 mm 196 pin stPBGA  
package with 1 mm ball pitch.  
APPLICATIONS  
• Routers and Layer 3 Switches.  
• 3G Wireless Base Station Controllers.  
• DSLAM Uplinks.  
• WAN and Edge ATM switches.  
• LAN switches and hubs.  
• Processes duplex bit-serial 155.52  
Mbit/s STS-3c/STM-1 data streams  
with on-chip clock and data recovery  
and clock synthesis.  
• Packet switches and hubs.  
• Network Interface Cards and Uplinks.  
GENERAL  
• Complies with Bellcore GR-253-CORE  
(1995 Issue) jitter tolerance, jitter  
transfer and intrinsic jitter criteria.  
• Provides control circuitry required to  
comply with Bellcore GR-253-CORE  
WAN clocking requirements related to  
wander transfer, holdover and long  
term stability when using an external  
VCXO.  
• Provides a standard 5 signal IEEE  
1149.1 JTAG test port for boundary  
scan board test purposes.  
• Provides a generic 8-bit  
microprocessor bus interface for  
configuration, control and status  
monitoring.  
BLOCK DIAGRAM  
Section/  
Line DCC  
Insertion  
Tx  
POS Frame  
Processor  
Tx  
Tx  
Tx  
Section O/H  
Processor  
Line O/H  
Processor  
Path O/H  
Processor  
Tx  
ATM Cell  
Processor  
UTOPIA Level 1  
8-bit x 52 MHz  
155.52 Mbit/s  
WAN  
Synch.  
Section  
Trace Buffer  
Path  
Trace Buffer  
UTOPIA Level 2  
POS-PHY Level 2  
16-bit x 52 MHz  
Rx  
ATM Cell  
Processor  
Rx  
Rx  
Rx  
Section O/H  
Processor  
Line O/H  
Processor  
Path O/H  
Processor  
Rx  
POS Frame  
Processor  
Section/  
Line DCC  
Extraction  
Sync Status,  
BERM  
External  
APS  
Interface  
JTAG Test  
Access Port  
Microprocessor Interface  
16-bit  
Microprocessor  
Bus  
Test Data  
PMC-2011690 (A1)  
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE  
© Copyright PMC-Sierra, Inc. 2001.  
12

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