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PM5384

更新时间： 2024-01-12 01:55:04

品牌	Logo	应用领域
PMC		异步传输模式 ATM
页数	文件大小	规格书
2页	33K
描述
Single Channel OC-3c ATM and POS Physical Layer Device

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PM5384 数据手册

PM5384

S/UNI®-1x155

Advance

Single Channel OC-3c ATM and POS Physical Layer Device

• Provides a UTOPIA Level 2, 8-bit wide

system interface (clocked up to 52

MHz) with parity support for ATM

applications.

• Provides a UTOPIA Level 2, 16-bit

wide system interface (clocked up to

52 MHz) with parity support for ATM

applications.

• Provides a SATURN POS-PHY Level

2, 16-bit system interface (clocked up

to 52 MHz) for Packet over

SONET/SDH (POS) applications

(similar to UTOPIA Level 2, but

adapted for packet transfer).

• Provides support functions for 1+1

APS operation.

• Low power 2.5/3.3 V CMOS with 5 V

FEATURES

• Single chip ATM and Packet over

SONET/SDH Physical Layer Device

operating at 155.52 Mbit/s.

• Implements the ATM Forum User

Network Interface (UNI) and the ATM

physical layer for Broadband ISDN

according to CCITT Recommendation

I.432.

• Implements Point-to-Point Protocol

(PPP) over SONET/SDH according to

RFC 2615.

TTL-compatible digital inputs/outputs

(PECL inputs/outputs are 3.3 V and

5 V compatible).

• Industrial temperature range (-40°C to

+85°C).

• 15 mm x15 mm 196 pin stPBGA

package with 1 mm ball pitch.

APPLICATIONS

• Routers and Layer 3 Switches.

• 3G Wireless Base Station Controllers.

• DSLAM Uplinks.

• WAN and Edge ATM switches.

• LAN switches and hubs.

• Processes duplex bit-serial 155.52

Mbit/s STS-3c/STM-1 data streams

with on-chip clock and data recovery

and clock synthesis.

• Packet switches and hubs.

• Network Interface Cards and Uplinks.

GENERAL

• Complies with Bellcore GR-253-CORE

(1995 Issue) jitter tolerance, jitter

transfer and intrinsic jitter criteria.

• Provides control circuitry required to

comply with Bellcore GR-253-CORE

WAN clocking requirements related to

wander transfer, holdover and long

term stability when using an external

VCXO.

• Provides a standard 5 signal IEEE

1149.1 JTAG test port for boundary

scan board test purposes.

• Provides a generic 8-bit

microprocessor bus interface for

configuration, control and status

monitoring.

BLOCK DIAGRAM

Section/

Line DCC

Insertion

POS Frame

Processor

Section O/H

Processor

Line O/H

Processor

Path O/H

Processor

ATM Cell

Processor

UTOPIA Level 1

8-bit x 52 MHz

155.52 Mbit/s

WAN

Synch.

Section

Trace Buffer

Path

Trace Buffer

UTOPIA Level 2

POS-PHY Level 2

16-bit x 52 MHz

ATM Cell

Processor

Section O/H

Processor

Line O/H

Processor

Path O/H

Processor

POS Frame

Processor

Section/

Line DCC

Extraction

Sync Status,

BERM

External

APS

Interface

JTAG Test

Access Port

Microprocessor Interface

16-bit

Microprocessor

Bus

Test Data

PMC-2011690 (A1)

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE

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