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PM5370-FI PDF预览

PM5370-FI

更新时间: 2024-02-27 06:16:38
品牌 Logo 应用领域
PMC /
页数 文件大小 规格书
2页 211K
描述
Telecom IC,

PM5370-FI 技术参数

生命周期:Obsolete包装说明:,
Reach Compliance Code:unknown风险等级:5.4

PM5370-FI 数据手册

 浏览型号PM5370-FI的Datasheet PDF文件第2页 
PM5370 WSE 40  
SONET/SDH Wideband Cross-Connect  
Released Product Brief  
SONET/SDH Overhead Accessibility  
Product Highlights  
Multi-purpose SONET/SDH VT/TU and SONET/SDH STS/STM cross-  
Supports extraction of the transport overhead (TOH) from the  
ingress ports (both high and low-speed) as well as the insertion  
of transport overhead into the egress ports via low bandwidth  
two-bit 77.76 MHz interfaces  
connect  
With a memory-switch architecture, implements a strictly non-  
blocking switch that supports a VT/TU level fabric of up to  
45 Gbit/s  
APS Features  
Supports a hardware-based Automatic Protection Switching  
mechanism (MAPS) for centralized link protection control when  
operating with other PMC-Sierra devices such as the PM5369  
TUPP 9953  
Supports 18 high-speed Enhanced SONET Serial Interface (ESSI)  
CML links each independently configurable for STS-48/STM-16  
at 2.488 Gbit/s or STS-12/STM-4 at 622.08 Mbit/s operation  
Supports system frame synchronization using an external frame  
pulse or ESSI smart frame synchronization using the frame  
boundary of the receive links  
Provides fully automatic protection switching for Class 1  
protection services including 1+1 protection, UPSR, SNCP, and  
static mesh protection services  
Compensates for differences in frame boundary arrival times  
between ingress ports using FIFOs and device level software  
configurable delay registers  
Provides hardware assists for Class 2 protection services  
including 1:N protection, BLSR-2/4, MSSPRING-2/4, and dynamic  
mesh protection schemes  
Each SONET STS-1 or SDH VC3/VC4-TUG3 may be independently  
configured as a single unit and/or as a container of VT/TUs. The  
contents may be switched intact or switched as VT/TUs  
I/O and General  
All high-speed ingress and egress links are 1.2 V CML and are  
ELVDS-compatible with programmable pre-emphasis on  
transmit, equalization on receive, and support for both AC and  
DC coupled interfaces  
Allows each SONET VT Group to be independently configured  
to carry VT1.5, VT2, VT3, or VT6 tributaries  
Allows each SDH TUG2 to be independently configured to carry  
TU11, TU12, or TU2 tributaries  
Each high-speed link supports SONET/SDH framed or unframed  
PRBS-23 or PRBS-7 generation and monitoring for off-line link  
verification  
Provides a device latency of 5.62 (+/-0.17) μs for 2.488 Gbit/s  
links and 6.21 (+/-0.67) μs for 622 Mbit/s links  
Block Diagram  
TOH Extraction I/F  
2 x 77.76 MHz  
TOH Insertion I/F  
2 x 77.76 MHz  
CML Interface  
18 x 2488 MHz or  
18 x 622 MHz  
45G STS/STM/VT/  
TU Memory Switch  
Core  
CML Interface  
18 x 2488 MHz or  
18 x 622 MHz  
Overhead  
Extraction  
Logic  
Overhead  
Insertion  
Logic  
Protection  
Switching  
Processor  
Receive  
Interface  
Transmit  
Interface  
Connection Map  
PMC-2020097, Issue 6  
© Copyright PMC-Sierra, Inc. 2004  
All rights reserved. Proprietary and Confidential to PMC-Sierra, Inc. and for its customers’ internal use.  

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