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PM5350 PDF预览

PM5350

更新时间: 2024-11-08 22:44:23
品牌 Logo 应用领域
PMC 网络接口
页数 文件大小 规格书
2页 50K
描述
155 Mb/s SATURN User Network Interface

PM5350 数据手册

 浏览型号PM5350的Datasheet PDF文件第2页 
PM5350  
PMC-Sierra,Inc.  
S/UNI-155-ULTRA  
155 Mb/s SATURN User Network Interface  
Compatible with ATM Forum UTOPIA  
interface format.  
Provides a generic 8-bit  
Operates in timing master or timing  
slave (loop timed) modes.  
Frames to SONET/SDH framing bytes  
(A1, A2), processes the section and  
FEATURES  
• Low-cost, monolithic SATURN®  
SONET/SDH ATM User Network  
Interface (UNI) for category-5 (UTP-5),  
microprocessor bus interface for  
configuration, control, and monitoring.  
Provides TTL-compatible inputs and  
outputs and differential PECL inputs.  
Low power, +5 V CMOS technology.  
Packaged in a 128-pin, 14 mm by  
20 mm Plastic Quad Flat Pack (PQFP)  
with 0.5 mm lead pitch.  
line Bit Interleaved Parity (B1, B2) and  
Shielded Twisted Pair (STP) and  
the Far-End Block Error (Z2) bytes.  
optical applications.  
Interprets the H1, H2, and H3 payload  
Implements the ATM Transmission  
pointer bytes.  
Convergence (TC) sublayer according  
to ATM Forum specifications using the  
Processes the SONET path overhead  
BIP-8 (B3), signal label (C2) and path  
SONET/SDH 155.52 Mb/s STS- 3c/  
status (G1) bytes.  
STM-1 and 51.84 Mb/s STS-1 formats.  
Inserts and extracts ATM payloads  
Provides on-chip UTP/STP drivers,  
using ATM cell delineation.  
APPLICATIONS  
155.52 or 51.84 Mb/s twisted pair or  
optical ATM LANs  
Workstations and Personal Computer  
NIC Cards  
Switches, Hubs, and Router Port  
Cards  
SONET- or SDH-Compliant ATM UNIs  
receivers, and line equalizers to allow  
Provides on-chip FIFO buffers in both  
transmit and receive paths.  
Provides on-chip support for GFC and  
XOFF flow control.  
Provides a synchronous 8-bit plus  
parity SATURN-Compliant Interface for  
PHYsical layer devices (SCI-PHY)  
bus operating at 50 MHz.  
direct connection to 155 Mb/s UTP-5  
or STP twisted pair wiring facilities  
using line coupling transformers.  
Provides a selectable UTP/STP or  
Pseudo-ECL (PECL) interface to allow  
direct connection to Optical Data Links  
(ODLs).  
Includes clock recovery and clock  
synthesis with on-chip loop filters.  
BLOCK DIAGRAM  
TSOC  
Clock  
Generator  
TXPRTY  
Transmit  
Transmit  
ATM  
4-Cell FIFO  
Transmit  
ATM Cell  
Processor  
TDAT[7:0]  
TCA  
Parallel  
to  
Serial  
TXD+  
Framer and  
Overhead  
Processor  
Twisted  
Pair Tx  
TXD-  
TWRENB  
TFCLK  
Analog Edge  
RSOC  
RXPRTY  
RDAT[7:0]  
RCA  
Receive  
Framer and  
Overhead  
Processor  
Receive  
ATM Cell  
Processor  
Serial  
to  
Parallel  
Receive  
ATM  
4-Cell FIFO  
RXD+  
RXD-  
Twisted  
Pair Rx  
Clock/Data  
Recovery  
RRDENB  
RFCLK  
TSEN  
SD  
LED  
Control  
Microprocessor  
Interface  
PMC-960709 (R4)  
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE  
1998 PMC-Sierra, Inc.  

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