Datasheet > PM4323-BI

PM4323-BI

更新时间： 2024-11-12 19:22:15

品牌	Logo	应用领域
PMC		/
页数	文件大小	规格书
2页	33K
描述
Telecom IC, CMOS, PBGA288,

阅读下载

中文翻译

获取价格

技术参数
数据手册

如果您发现信息不准确，欢迎纠错

PM4323-BI 技术参数

是否Rohs认证：	不符合	生命周期：	Transferred
Reach Compliance Code：	compliant	风险等级：	5.72
JESD-30 代码：	S-PBGA-B288	JESD-609代码：	e0
湿度敏感等级：	3	端子数量：	288
最高工作温度：	85 °C	最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY	封装代码：	BGA
封装等效代码：	BGA288,22X22,40	封装形状：	SQUARE
封装形式：	GRID ARRAY	电源：	1.8,3.3 V
认证状态：	Not Qualified	子类别：	Other Telecom ICs
表面贴装：	YES	技术：	CMOS
温度等级：	INDUSTRIAL	端子面层：	Tin/Lead (Sn/Pb)
端子形式：	BALL	端子节距：	1 mm
端子位置：	BOTTOM	Base Number Matches：	1

PM4323-BI 数据手册

PM4323

OCTLIU LT

Octal T1/E1/J1 Low Latency Transport Line Interface Device

• Provides a selectable, per channel

independent de-jittered T1 or E1

recovered clock for system timing and

redundancy.

• Provides PRBS generators and

detectors on each tributary for error

testing at DS1 and E1 rates as

recommended in ITU-T O.151.

• Uses line rate system clock.

• Recovers clock and data using a digital

phase locked loop for high jitter

tolerance.

• Tolerates more than 0.4 UI peak-to-

peak high frequency jitter as required

by AT&T TR 62411 and Bellcore

TR-TSY-000170.

• Outputs dual rail recovered line pulses,

a single rail DS-1/E1 signal, or parallel

data in SBI/SBI TR bus format.

• Performs B8ZS or AMI decoding when

processing a bipolar DS-1 signal and

HDB3 or AMI decoding when

processing a bipolar E1 signal.

• Detects line code violations (LCVs),

B8ZS/HDB3 line code signatures, and

four (E1), eight (T1+B8ZS), or sixteen

(T1 AMI) successive zeros.

FEATURES

• Monolithic device integrating eight

T1/J1 or E1 short haul and long haul

line interface units.

• Software switchable between T1/J1

and E1 operation on a per-device

basis.

• Meets or exceeds T1/J1 and E1 short

haul and long haul network access

specifications including ANSI T1.102,

T1.403, T1.408, AT&T TR 62411,

ITU-T G.703, G.704 as well as

ETSI 300-011, TBR 4, TBR 12, and

TBR 13. In conjunction with the

TEMAP 84 (PM5366), allows Add Drop

Multiplexers and Terminal Multiplexers

to meet GR253, GR496, and G.783.

• Optional encoding/decoding of B8ZS,

HDB3, and AMI line codes.

• Provides receive equalization, clock

recovery, and line performance

monitoring.

• Provides transmit and receive jitter

attenuation.

SYSTEM INTERFACE

• Supports transfer of transmitted single

rail PCM and signaling data from

1.544 Mbit/s and 2.048 Mbit/s

backplane buses or a SBI/SBI TR

interface for low pin count

interconnection of up to 11 OCTLIU

LTs to the high-density PM5366

TEMAP 84 T1/E1 framer.

• Provides a programmable depth FIFO

buffer for jitter attenuation, rate

conversion, and latency optimization in

the receive path.

RECEIVE SECTION

• Supports T1/E1 signal reception for

distances with up to 36 dB of cable

attenuation at nominal conditions using

PIC 22 gauge cable emulation.

• Supports G.772 compliant

non-intrusive protected monitoring

points.

TRANSMIT SECTION

• Generates DSX-1 short haul and DS-1

long haul pulses with programmable

pulse shape compatible with AT&T,

ANSI, and ITU requirements.

• Provides digitally programmable long

haul and short haul line build out.

BLOCK DIAGRAM

TDN[8:1]

TDP[8:1]

TCLK[8:1]

DSYNC

DDATA[7:0]

SBI TR

Extract

DLINKRATE[5:0]

DPARITY

DALARM

TXTIP1[8:1]

LCODE

XIBC

TJAT

XPDE

TXTIP2[8:1]

XLPG

AMI / B8ZS /

HDB3 Line

Encoder

Inband Loop-

back Code

Generator

DVALID

DFULL

Digital Jitter

Attenuator

Pulse Density

Enforcer

Transmit LIU

TXRING1[8:1]

TXRING2[8:1]

PISO

DC1FP

DDATA[7:0]

DDP

SBI

(Diagnostic

Extract

Digital

DPL

DV5

Loopback)

PRBS

Pattern

PMON

Performance

Monitor

REFCLK

Generator /

Detector

C1FPOUT

ADATA[7:0]

ADP

(Line

Loopback)

SBI

Insert

APL

AV5

IBCD

RXTIP[8:1]

RJAT

CDRC

PDVD

AACTIVE

RLPS

Inband Loop

back Code

Detector

Digital Jitter

Attenuator

Clk/Data

Pulse Density

Viol. Detector

AC1FP

Receive LIU

SIPO

Recovery

RXRING[8:1]

ADATA[7:0]

ALINKRATE[5:0]

SBI TR

Insert

APARITY

AALARM

AVALID

ASYNC

LIU Octant x 8

CSD

RDP[8:1]

TOPS

XCLK

Clock

RDN/RLCV[8:1]

RCLK[8:1]

Timing

Synthesis /

Distribution

RSYNC

Options

LOS

TXHIZ/LineLB

Serial

H/W only

uP Interface

JTAG

Output

Auto-config

SBI_EN

RSTB

PMC-2022058 (R3)

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE

中文翻译

下载PDF

与PM4323-BI相关器件

型号	品牌	获取价格	描述	数据表
PM4325	PMC	获取价格	Octal Short Haul T1/E1/J1 Low Latency Transport Line Interface
PM432-670.00M	CONNOR-WINFIELD	获取价格	LVPECL Output Clock Oscillator, 670MHz Nom, ROHS COMPLIANT, HERMETIC SEALED, CERAMIC PACKA
PM432-673.0M	CONNOR-WINFIELD	获取价格	Oscillator
PM43-270K-RC	BOURNS	获取价格	SMD Power Inductor
PM43-270M	ETC	获取价格	SMT Power Inductors
PM43-270M-RC	BOURNS	获取价格	General Purpose Inductor, 27uH, 20%, 1 Element, Ferrite-Core, SMD, 1816, ROHS COMPLIANT
PM4328	PMC	获取价格	HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED M13 MULTIPLEXER
PM4328?	ETC	获取价格	Data Sheet Errata\|PMC-2011799 [191 kB]?
PM4328-PI	PMC	获取价格	HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED M13 MULTIPLEXER
PM4329	MICROSEMI	获取价格	Telecom IC, CMOS, PBGA276,

与PM4323-BI相关文章

国产厂商思特威CMOS图像传感器芯片单月出货超1亿颗，技术创新引领行业发展
2024-11-14

23
台积电5nm和3nm产能利用率达100%，半导体行业景气度持续攀升
2024-11-14

8
AMD宣布全球裁员约1000人，调整战略聚焦增长
2024-11-14

9
英伟达新AI芯片Rubin或提前半年亮相
2024-11-05

32

产品中心

服务支持

精选活动

关于我们

帮助中心

PM4323-BI

PM4323-BI 技术参数

PM4323-BI 数据手册

与PM4323-BI相关器件

与PM4323-BI相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

PM4323-BI

PM4323-BI 技术参数

PM4323-BI 数据手册

与PM4323-BI相关器件

与PM4323-BI相关文章

您还可以找

您在本页遇到什么问题？