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PM4319

更新时间: 2024-09-22 21:54:15
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描述
OCTAL T1/E1/J1 Short Haul Line Interface Device

PM4319 数据手册

 浏览型号PM4319的Datasheet PDF文件第2页 
PM4319  
OCTLIU-SH  
Preliminary  
OCTAL T1/E1/J1 Short Haul Line Interface Device  
testing at DS1 and E1 rates as  
recommended in ITU-T O.151.  
SYSTEM INTERFACE  
FEATURES  
• High-density SBI bus interface.  
Supports seamless interconnection of  
up to 11 OCTLIU-SHs to TE-32,  
TEMAP-84 and AAL1gator-32 using  
only 27 wires.  
Monolithic device which integrates 8  
T1/J1 or E1 short haul line interface  
circuits.  
• Provides an 8-bit microprocessor bus  
interface for configuration, control, and  
status monitoring.  
Software-selectable between T1/J1 and  
E1 operation on a per-device basis.  
Provides line and digital loopback modes.  
• Supports programmable inband  
loopback codes.  
RECEIVE SECTION  
• Meets or exceeds T1/J1 and E1 short  
haul network access specifications  
including ANSI T1.102, T1.403,  
T1.408, AT&T TR 62411, ITU-T G.703,  
G.704 as well as ETSI 300-011, CTR-  
4, CTR-12 and CTR-13.  
• Supports T1 signal reception at 772  
kHz and E1 signal reception at 1.024  
MHz for distances with up to 6 dB of  
cable attenuation.  
• Uses line rate system clock.  
• Provides an IEEE 1149.1 (JTAG)  
compliant test access port (TAP) and  
controller for boundary scan test.  
• Performs B8ZS or AMI decoding when  
processing a bipolar DS-1 signal, and  
HDB3 decoding when processing a  
bipolar E1 signal.  
• Provides encoding and decoding of  
B8ZS, HDB3 and AMI line codes.  
• Provides a microprocessor-readable  
general purpose input pin and a  
microprocessor-writable general  
purpose output pin.  
• Provides clock recovery and line  
performance monitoring.  
• Tolerates more than 0.3 UI peak-to-  
peak, high frequency jitter as required  
by AT&T TR 62411 and Bellcore TR-  
TSY-000170.  
• Provides transmit and receive jitter  
attenuation.  
POWER  
• Implemented in a low power 3.3 V  
tolerant 1.8/3.3 V CMOS technology.  
• Provides support for redundancy.  
• Detects line code violations, B8ZS/  
HDB3 line code signatures, loss of  
signal, and successive zeroes  
conditions.  
• Provides digitally programmable pulse  
templates.  
PACKAGE  
Available in a high density 288-pin  
• Provides a selectable, per channel  
independent de-jittered T1 or E1  
recovered clock for system timing and  
redundancy.  
Tape-SBGA (23 mm x 23 mm) package.  
• Supports G.772 compliant non-  
intrusive protected monitoring points.  
• Provides a -40 °C to +85 °C industrial  
temperature operating range.  
• Provides PRBS generators and  
detectors on each tributary for error  
BLOCK DIAGRAM  
TXTIP1[8:1]  
TXTIP2[8:1]  
LCODE  
XIBC  
TJAT  
XPDE  
XLPG  
Transmit LIU  
AMI / B8ZS /  
HDB3 Line  
Encoder  
Inband Loop-  
back Code  
Generator  
Digital Jitter  
Attenuator  
Pulse Density  
Enforcer  
TXRING1[8:1]  
TXRING2[8:1]  
ADATA[7:0]  
Tx Data  
EXSBI-8  
ADP  
APL  
AV5  
SBI Extract  
Tx Clock  
(Diagnostic  
Digital  
Loopback)  
PRBS  
Pattern  
Generator /  
Detector  
REFCLK  
AC1FP  
DC1FP  
PMON  
Performance  
Monitor  
(Line  
C1FPOUT  
DDATA[7:0]  
DDP  
Loopback)  
Rx Data  
INSBI-8  
IBCD  
RXTIP[8:1]  
RJAT  
CDRC  
PDVD  
RLPS  
Receive LIU  
-
SBI Insert  
DPL  
Inband Loop  
back Code  
Detector  
Digital Jitter  
Attenuator  
Clk/Data  
Recovery  
Pulse Density  
Viol. Detector  
Rx Clock  
DV5  
RXRING[8:1]  
DACTIVE  
LIU Octant x 8  
TXHIZ/LLB  
RSTB  
CSD  
TOPS  
LOS  
XCLK  
Clock  
Synthesis /  
Distribution  
Timing  
Options  
Serial  
Output  
RSYNC  
JTAG  
uP Interface  
PMC-2012171 (p2)  
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE  
© Copyright PMC-Sierra, Inc. 2001  

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