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PM3386

更新时间: 2024-11-14 22:44:23
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PMC 控制器以太网
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2页 47K
描述
Dual Gigabit Ethernet Controller

PM3386 数据手册

 浏览型号PM3386的Datasheet PDF文件第2页 
PM3386  
S/UNI®-2xGE  
Dual Gigabit Ethernet Controller  
Minimum frame size 64 bytes. Supports  
jumbo frames up to 9.6 kbytes.  
Minimum 58 minutes before rollover.  
Provides statistic counters to support  
SNMP and RMON implementations.  
FEATURES  
Two port full-duplex Gigabit Ethernet  
Controller with an industry standard  
POS-PHY Level 3system interface.  
Provides direct connection to optics.  
Connection to copper Gigabit Ethernet  
physical layer devices via two GMII  
interfaces.  
Incorporates dual SERDES,  
compatible to IEEE 802.3 1998 PMA  
physical layer specification.  
Supports big endian data formats.  
Programmable inter-packet gap (IPG).  
Loopback for diagnostic capability  
through GMAC.  
POS-PHY LEVEL 3 SYSTEM  
INTERFACE  
Standard OC-48 bandwidth  
FLOW CONTROL  
Packet/Cell interface.  
Option to support IEEE 802.3-1998  
flow control at each Ethernet port.  
Programmable watermarks for  
full/empty FIFO conditions.  
Compatible with PMC-Sierra devices  
supporting POS-PHY Level 3, including:  
PM5381 S/UNI®-2488 ATM and  
POS physical layer device.  
Supports dual IEEE 802.3 -1998  
GMII/TBI interfaces for connection to  
copper Gigabit Ethernet physical layer  
devices.  
Provides dual standard IEEE 802.3  
Gigabit Ethernet MACs for frame  
verification.  
Provides on-chip data recovery and  
clock synthesis.  
Provides eight unicast exact-match  
address filters to filter frames based on  
DA, SA, or VID.  
Automatic generation of pause frames  
based on FIFO fill levels.  
Upper layer device can flow control  
Ethernet ports using side-band or host  
signaling to cause generation of a  
Pause frame.  
Provides per-port side-band Pause  
state indication for upstream devices.  
Loss-less flow control on all valid  
frames up to 9.6 kbytes.  
PM5358 S/UNI®-4x622 single  
channel OC-48c device with  
integrated analog.  
PM7390 S/UNI-MACH-48 multi-  
service access device for  
channelized interfaces.  
PM5382 S/UNI-16x155 sixteen  
channel OC-3c framer with  
integrated analog and POS-PHY  
Level 3 and UTOPIA Level 3  
interface.  
STATISTICS  
POS-PHY Level 3 provides connection  
to upper layer device at data rates up  
to 2,400 Mbit/s.  
Each address filter can indicate  
whether to accept or discard based on  
a match.  
40 bit counters are used to ensure  
rollover compliance with  
IEEE 802.3-1998.  
Provides 64-group multicast address  
filter.  
Internal 16 kbyte TX and 64 kbyte RX  
FIFOs to accommodate system  
latencies.  
BLOCK DIAGRAM  
POS-PHY  
Level 3  
PAUSE [1:0]  
Ethernet Statistics  
PAUSED [1:0]  
SATURN® compatible interface for  
Packet-Over-SONET Physical Layer  
and Link Layer devices Level 3 (POS-  
PHY Level 3 system interface).  
Line side loopback for system level  
diagnostic capability.  
16 bit generic microprocessor interface  
for device initialization, control, register  
and per port statistics access.  
MDC  
MDIO  
RFCLK  
Ingress  
Interface  
RENB  
Enhanced Gigabit MAC  
RX_CLK  
RX_DV  
RX_ER  
RDAT[31:0]  
RMOD[1:0]  
Address  
Filtering  
Flow Ctrl /  
Auto-Negotiation  
RPRTY  
RVAL  
RXD [7:0]  
GMII  
Interface  
POS  
PHY  
Ingress  
FIFO  
RSOP  
REOP  
GTX_CLK  
TX_EN  
TX_ER  
RERR  
RSX  
TXD [7:0]  
Gigabit  
Media  
Access  
Controller  
DTPA[1:0]  
STPA  
Data Recovery/  
Serial to Parallel  
Egress  
Interface  
RXD +/-  
GIGABIT ETHERNET MAC  
PTPA  
TADR  
TFCLK  
TENB  
Verifies frame integrity (FCS and  
length checks).  
8B/10B  
Encoder/  
Decoder  
SD  
PLL Clock  
Multiply  
CLK125  
TDAT[31:0]  
Errored frames can be filtered or  
passed to a higher layer device.  
Automatic Base Page Autonegotiation,  
extended Autonegotiation (Next Page)  
supported via host.  
TMOD[1:0]  
TPRTY  
TSOP  
POS  
PHY  
Egress  
FIFO  
TXD +/-  
Parallel to Serial  
TEOP  
TERR  
SERDES  
PCS  
MAC  
ATP[3:0]  
TSX  
Egress Ethernet frame encapsulation  
(pad to minimum size, add preamble,  
IFG and CRC generation).  
Microprocessor  
Interface  
JTAG  
Supports Ethernet 2.0, IEEE 802.3 LLC  
and IEEE 802.3 SNAP/LLC encoding  
formats, and VLAN tagged frames.  
PMC-1991223 (R4)  
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERSINTERNAL USE  
© Copyright PMC-Sierra, Inc. 2001  

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