PLS101

更新时间： 2024-11-12 22:26:27

品牌	Logo	应用领域
恩智浦 - NXP		可编程逻辑
页数	文件大小	规格书
8页	131K
描述
Programmable logic arrays 16 】 48 】 8

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PLS101 数据手册

Philips Semiconductors Programmable Logic Devices

Product specification

Programmable logic arrays

(16 × 48 × 8)

PLS100/PLS101

DESCRIPTION

FEATURES

PIN CONFIGURATIONS

The PLS100 (3-State) and PLS101 (Open

Collector) are bipolar, fuse Programmable

Logic Arrays (PLAs). Each device utilizes the

standard AND/OR/Invert architecture to

directly implement custom sum of product

equations.

• Field-programmable (Ni-Cr link)

• Input variables: 16

N Package

FE*

• Output functions: 8

27 I8

• Product terms: 48

26 I9

Each device consists of 16 dedicated inputs

and 8 dedicated outputs. Each output is

capable of being actively controlled by any or

all of the 48 product terms. The True,

Complement, or Don’t Care condition of each

of the 16 inputs and be ANDed together to

comprise one P-term. All 48 P-terms can be

selectively ORed to each output.

• I/O propagation delay: 50ns (max.)

• Power dissipation: 600mW (typ.)

• Input loading: –100µA (max.)

• Chip Enable input

25 I10

24 I11

23 I12

I13

21 I14

I15

• Output option:

– PLS100: 3-State

19 CE

18 F0

17 F1

16 F2

15 F3

The PLS100 and PLS101 are fully TTL

compatible, and chip enable control for

expansion of input variables and output

inhibit. They feature either Open Collector or

3-State outputs for ease of expansion of

product terms and application in

– PLS101: Open-Collector

• Output disable function:

– 3-State: Hi-Z

– Open-Collector: High

GND 14

bus-organized systems.

Fuse Enable Pin: It is recommended that this pin

be left open or connected to ground during normal

operation.

Order codes are listed in the Ordering

Information Table.

APPLICATIONS

• CRT display systems

N = Plastic DIP (600mil-wide)

• Code conversion

• Peripheral controllers

• Function generators

• Look-up and decision tables

• Microprogramming

A Package

I5 I6 I7

I8 I9

28 27 26

I10

I11

I12

• Address mapping

• Character generators

• Data security encoders

• Fault detectors

I13

I14

I15

• Frequency synthesizers

• 16-bit to 8-bit bus interface

• Random logic replacement

12 13 14 15 16 17 18

GND

F1 F0

F5 F4

F3 F2

A = Plastic Leaded Chip Carrier

ORDERING INFORMATION

DESCRIPTION

3-STATE

PLS100N

PLS100A

OPEN COLLECTOR

PLS101N

DRAWING NUMBER

0413D

28-Pin Plastic Dual In-Line 600mil-wide

28-Pin Plastic Leaded Chip Carrier

PLS101A

0401F

October 22, 1993

853–0308 11164

12 3 4 5 6 7 8

中文翻译

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与PLS101相关器件

型号	品牌	获取价格	描述	数据表
PLS101A	NXP	获取价格	Programmable logic arrays 16 】 48 】 8
PLS101A	YAGEO	获取价格	OT PLD, 50ns, TTL, PQCC28
PLS101F	PHILIPS	获取价格	OT PLD, PLA-Type, TTL, CDIP28
PLS101N	NXP	获取价格	Programmable logic arrays 16 】 48 】 8
PLS101N	YAGEO	获取价格	OT PLD, 50ns, TTL, PDIP28
PLS101N-B	ETC	获取价格	Fuse-Programmable PLD
PLS103A	PHILIPS	获取价格	OT PLD, PAD-Type, TTL, PQCC28
PLS103A	NXP	获取价格	IC FPGA, PQCC28, Field Programmable Gate Array
PLS103F	PHILIPS	获取价格	OT PLD, PAD-Type, TTL, CDIP28
PLS103FB	PHILIPS	获取价格	OT PLD, PAD-Type, TTL, CDIP28

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