Datasheet > PLL2013X

PLL2013X

更新时间： 2024-09-20 23:28:43

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PLL2013X 20MHZ~170MHZ FSPLL PLL2013X\|Data Sheet

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PLL2013X 数据手册

20MHz ~ 170MHz FSPLL

PLL2013X

General Description

Features

The PLL2013X is a Phase-Locked Loop (PLL) frequency

synthesizer constructed in CMOS on single monolithic

structure. The PLL macro-functions provide frequency

multiplication capabilities.

• 0.25mm CMOS device technology

• 2.5 Volt single power supply

• Output frequency range: 20 ~ 170 MHz

• Jitter ±150ps at 170MHz

• Duty ratio 45% to 55%(All tuned range)

• Frequency changed by programmable

divider

The output clock frequency Fout is related to the input

clock frequency Fin(XTALIN) by the following

equation:

Fout=(m*Fin)/(p*2^s)

• Provision for 14.318Mhz crystal oscillator

buffer - OPTION

Where, Fout is the output clock frequency.

• Power down mode

Fin is the input clock frequency.

m,p and s are the values for programmable dividers.

PLL2013X consists of a phase/Frequency Detector(PFD),

a Charge Pump an External Loop Filter, a Voltage

Controlled Oscillator(VCO), a 6bit Pre-divider, an 8bit

Main divider and 2bit Post Scaler as shown inFigure1.

IMPORTANT NOTICE

- Please contact SEC application engineer to confirm the proper selection of M,P,S value.

FUNCTIONAL BLOCK DIAGRAM

FOUT

FIN

Pre Divider

PFD

Charge

Pump

VCO

Post Scaler

Loop

Filter

Main Divider

Figure 1. Phase Locked Loop Block Diagram

NOTE

• Xtal oscillator is OPTIONAL block.

If customer concerns about this block - xtal buffer or lock detector, refer to next chapter.

Ver 2.3 ( DEC. 1999 )

No responsibility is assumed by SEC for its use nor for

any infringements of patents or other rights of third parties

that may result from its use. The contents of the datasheet

is subject to change without any notice.

SAMSUNG ELECTRONICS Co. LTD

12 3 4 5 6 7...15

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