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PLHS501IA-T

更新时间： 2024-09-20 19:56:35
品牌 Logo 应用领域
恩智浦 - NXP 输入元件可编程逻辑
页数 文件大小 规格书
12页 84K
描述
OT PLD, PQCC52

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中文翻译

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PLHS501IA-T 技术参数

生命周期：Obsolete包装说明：QCCJ,
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.84JESD-30 代码：S-PQCC-J52
长度：19.1262 mm专用输入次数：24
I/O 线路数量：8端子数量：52
最高工作温度：85 °C最低工作温度：-40 °C
组织：24 DEDICATED INPUTS, 8 I/O输出函数：COMBINATORIAL
封装主体材料：PLASTIC/EPOXY封装代码：QCCJ
封装形状：SQUARE封装形式：CHIP CARRIER
可编程逻辑类型：OT PLD认证状态：Not Qualified
座面最大高度：4.57 mm最大供电电压：5.5 V
最小供电电压：4.5 V标称供电电压：5 V
表面贴装：YES技术：TTL
温度等级：INDUSTRIAL端子形式：J BEND
端子节距：1.27 mm端子位置：QUAD
宽度：19.1262 mmBase Number Matches：1

PLHS501IA-T 数据手册

 浏览型号PLHS501IA-T的Datasheet PDF文件第2页浏览型号PLHS501IA-T的Datasheet PDF文件第3页浏览型号PLHS501IA-T的Datasheet PDF文件第4页浏览型号PLHS501IA-T的Datasheet PDF文件第5页浏览型号PLHS501IA-T的Datasheet PDF文件第6页浏览型号PLHS501IA-T的Datasheet PDF文件第7页 
Philips Semiconductors Programmable Logic Devices  
Product specification  
Programmable macro logic  
PML  
PLHS501/PLHS501I  
FEATURES  
PIN CONFIGURATION  
• Programmable Macro Logic device  
A Package  
(52-pin PLCC)  
• Full connectivity  
I
I
I
I
I
I
I
I
I
I
I
I
I
5
17 16 15 14 13 12 11 10  
9
8
7
6
• TTL compatible  
7
6
5
4
3
2
1
52 51 50 49 48 47  
8
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
V
V
I
• SNAP development system:  
CC  
CC  
9
I
– Supports third-party schematic entry  
18  
4
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
I
I
I
I
I
formats  
19  
3
I
– Macro library  
20  
2
1
0
I
– Versatile netlist format for design  
portability  
21  
I
22  
– Logic, timing, and fault simulation  
I
B
B
B
B
X
23  
3
2
1
0
B
4
• Delay per internal NAND function = 6.5ns  
B
5
(typ)  
B
6
• Testable in unprogrammed state  
B
7
7
6
• Security fuse allows protection of  
O
0
X
proprietary designs  
GND 20  
34 GND  
21 22 23 24 25 26 27 28 29 30 31 32 33  
O
O
O
O
O
O
O
X
X
X
X
X
X
4 5  
1
2
3
4
5
6
7
0
1
2
3
STRUCTURE  
• NAND gate based architecture  
– 72 foldback NAND terms  
ARCHITECTURE  
DESCRIPTION  
The core of the PLHS501 is a programmable  
fuse array of 72 NAND gates. The output of  
each gate folds back upon itself and all other  
NAND gates. In this manner, full connectivity  
of all logic functions is achieved in the  
PLHS501. Any logic function can be created  
within the core of the device without wasting  
valuable I/O pins. Furthermore, a speed  
advantage is acquired by implementing  
multi-level logic within a fast internal core  
without incurring any delays from the I/O  
buffers.  
The PLHS501 is a high-density Bipolar  
• 136 input-wide logic terms  
• 44 additional logic terms  
Programmable Macro Logic device. PML  
incorporates a programmable NAND  
structure. The NAND architecture is an  
efficient method for implementing any logic  
function. The SNAP software development  
system provides a user friendly environment  
for design entry. SNAP eliminates the need  
for a detailed understanding of the PLHS501  
architecture and makes it transparent to the  
user. PLHS501 is also supported on the  
Philips Semiconductors SNAP software  
development systems.  
• 24 dedicated inputs (I – I  
)
0
23  
• 8 bidirectional I/Os with individual 3-State  
enable:  
– 4 Active-High (B – B )  
4
7
– 4 Active-Low (B – B )  
0
3
• 16 dedicated outputs:  
– 4 Active-High outputs  
O , O with common 3-State enable  
0
1
O , O with common 3-State enable  
The PLHS501 is ideal for a wide range of  
microprocessor support functions, including  
bus interface and control applications.  
2
3
– 4 Active-Low outputs:  
O , O with common 3-State enable  
4
5
The PLHS501 is also processed to industrial  
requirements for operation over an extended  
temperature range of –40°C to +85°C and  
supply voltage of 4.5V to 5.5V.  
O , O with common 3-State enable  
6
7
– 8 Exclusive-OR outputs:  
X , X with common 3-State enable  
0
1
X , X with common 3-State enable  
2
3
X , X with common 3-State enable  
4
5
X , X with common 3-State enable  
6
7
PML is a trademark of Philips Semiconductors  
October 22, 1993  
1
853–1207 11164  
1234567...12

中文翻译

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