5秒后页面跳转
捷配首页

Datasheet > 可编程逻辑 > 可编程逻辑器件> PLHS501IA
PLHS501IA PDF预览

PLHS501IA

更新时间： 2024-11-07 22:06:15
品牌 Logo 应用领域
恩智浦 - NXP 可编程逻辑
页数 文件大小 规格书
12页 85K
描述
Programmable macro logic PML

阅读下载

中文翻译

获取价格

PLHS501IA 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：LCC包装说明：PLASTIC, LCC-52
针数：52Reach Compliance Code：unknown
HTS代码：8542.39.00.01风险等级：5.91
架构：PLE-TYPE最大时钟频率：30 MHz
JESD-30 代码：S-PQCC-J52长度：19.1262 mm
湿度敏感等级：1专用输入次数：24
I/O 线路数量：8输入次数：32
输出次数：24端子数量：52
最高工作温度：85 °C最低工作温度：-40 °C
组织：24 DEDICATED INPUTS, 8 I/O输出函数：COMBINATORIAL
封装主体材料：PLASTIC/EPOXY封装代码：QCCJ
封装等效代码：LDCC52,.8SQ封装形状：SQUARE
封装形式：CHIP CARRIER峰值回流温度（摄氏度）：225
电源：5 V可编程逻辑类型：OT PLD
传播延迟：17.5 ns认证状态：Not Qualified
座面最大高度：4.57 mm子类别：Programmable Logic Devices
最大供电电压：5.5 V最小供电电压：4.5 V
标称供电电压：5 V表面贴装：YES
技术：TTL温度等级：INDUSTRIAL
端子形式：J BEND端子节距：1.27 mm
端子位置：QUAD处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：19.1262 mmBase Number Matches：1

PLHS501IA 数据手册

 浏览型号PLHS501IA的Datasheet PDF文件第2页浏览型号PLHS501IA的Datasheet PDF文件第3页浏览型号PLHS501IA的Datasheet PDF文件第4页浏览型号PLHS501IA的Datasheet PDF文件第5页浏览型号PLHS501IA的Datasheet PDF文件第6页浏览型号PLHS501IA的Datasheet PDF文件第7页 
Philips Semiconductors Programmable Logic Devices  
Product specification  
Programmable macro logic  
PML  
PLHS501/PLHS501I  
FEATURES  
PIN CONFIGURATION  
• Programmable Macro Logic device  
A Package  
(52-pin PLCC)  
• Full connectivity  
I
I
I
I
I
I
I
I
I
I
I
I
I
5
17 16 15 14 13 12 11 10  
9
8
7
6
• TTL compatible  
7
6
5
4
3
2
1
52 51 50 49 48 47  
8
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
V
V
I
• SNAP development system:  
CC  
CC  
9
I
– Supports third-party schematic entry  
18  
4
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
I
I
I
I
I
formats  
19  
3
I
– Macro library  
20  
2
1
0
I
– Versatile netlist format for design  
portability  
21  
I
22  
– Logic, timing, and fault simulation  
I
B
B
B
B
X
23  
3
2
1
0
B
4
• Delay per internal NAND function = 6.5ns  
B
5
(typ)  
B
6
• Testable in unprogrammed state  
B
7
7
6
• Security fuse allows protection of  
O
0
X
proprietary designs  
GND 20  
34 GND  
21 22 23 24 25 26 27 28 29 30 31 32 33  
O
O
O
O
O
O
O
X
X
X
X
X
X
4 5  
1
2
3
4
5
6
7
0
1
2
3
STRUCTURE  
• NAND gate based architecture  
– 72 foldback NAND terms  
ARCHITECTURE  
DESCRIPTION  
The core of the PLHS501 is a programmable  
fuse array of 72 NAND gates. The output of  
each gate folds back upon itself and all other  
NAND gates. In this manner, full connectivity  
of all logic functions is achieved in the  
PLHS501. Any logic function can be created  
within the core of the device without wasting  
valuable I/O pins. Furthermore, a speed  
advantage is acquired by implementing  
multi-level logic within a fast internal core  
without incurring any delays from the I/O  
buffers.  
The PLHS501 is a high-density Bipolar  
• 136 input-wide logic terms  
• 44 additional logic terms  
Programmable Macro Logic device. PML  
incorporates a programmable NAND  
structure. The NAND architecture is an  
efficient method for implementing any logic  
function. The SNAP software development  
system provides a user friendly environment  
for design entry. SNAP eliminates the need  
for a detailed understanding of the PLHS501  
architecture and makes it transparent to the  
user. PLHS501 is also supported on the  
Philips Semiconductors SNAP software  
development systems.  
• 24 dedicated inputs (I – I  
)
0
23  
• 8 bidirectional I/Os with individual 3-State  
enable:  
– 4 Active-High (B – B )  
4
7
– 4 Active-Low (B – B )  
0
3
• 16 dedicated outputs:  
– 4 Active-High outputs  
O , O with common 3-State enable  
0
1
O , O with common 3-State enable  
The PLHS501 is ideal for a wide range of  
microprocessor support functions, including  
bus interface and control applications.  
2
3
– 4 Active-Low outputs:  
O , O with common 3-State enable  
4
5
The PLHS501 is also processed to industrial  
requirements for operation over an extended  
temperature range of –40°C to +85°C and  
supply voltage of 4.5V to 5.5V.  
O , O with common 3-State enable  
6
7
– 8 Exclusive-OR outputs:  
X , X with common 3-State enable  
0
1
X , X with common 3-State enable  
2
3
X , X with common 3-State enable  
4
5
X , X with common 3-State enable  
6
7
PML is a trademark of Philips Semiconductors  
October 22, 1993  
1
853–1207 11164  
1234567...12

中文翻译

下载PDF

与PLHS501IA相关器件

型号 品牌 获取价格 描述 数据表
PLHS501IA-T NXP

获取价格

 		OT PLD, PQCC52
PLHS502A NXP

获取价格

 		OT PLD, PQCC52
PLHS502A PHILIPS

获取价格

 		OT PLD, PLE-Type, TTL, PQCC68
PLHS502A YAGEO

获取价格

 		OT PLD, TTL, PQCC68,
PLHS502A-T YAGEO

获取价格

 		OT PLD, TTL, PQCC68,
PLHS601A YAGEO

获取价格

 		OT PLD, TTL, PQCC68,
PLHS601A-T YAGEO

获取价格

 		OT PLD, TTL, PQCC68,
PLI13M ETC

获取价格
PLI-13M ROHM

获取价格

 		Transistor Output Slotted Switch, 1-Channel, 1.2mm Slot Width
PLI13MA ETC

获取价格

与PLHS501IA相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证