PLC42VA12N

更新时间： 2024-11-10 22:12:51

品牌	Logo	应用领域
恩智浦 - NXP		可编程逻辑器件光电二极管输入元件时钟
页数	文件大小	规格书
20页	437K
描述
CMOS programmable multi-function PLD 42 】 105 】 12

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PLC42VA12N 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
零件包装代码：	DIP	包装说明：	DIP, DIP24,.3
针数：	24	Reach Compliance Code：	unknown
HTS代码：	8542.39.00.01	风险等级：	5.91
Is Samacsys：	N	其他特性：	PROGRAMMABLE MULTI-FUNCTION PLD; 1 EXTERNAL CLOCK; SHARED INPUT/CLOCK; REGISTER PRELOAD
架构：	PLS-TYPE	最大时钟频率：	14.9 MHz
JESD-30 代码：	R-PDIP-T24	长度：	31.7 mm
湿度敏感等级：	1	专用输入次数：	8
I/O 线路数量：	12	输入次数：	42
输出次数：	12	产品条款数：	105
端子数量：	24	最高工作温度：	75 °C
最低工作温度：		组织：	8 DEDICATED INPUTS, 12 I/O
输出函数：	MACROCELL	封装主体材料：	PLASTIC/EPOXY
封装代码：	DIP	封装等效代码：	DIP24,.3
封装形状：	RECTANGULAR	封装形式：	IN-LINE
峰值回流温度（摄氏度）：	225	电源：	5 V
可编程逻辑类型：	OT PLD	传播延迟：	55 ns
认证状态：	Not Qualified	座面最大高度：	4.7 mm
子类别：	Programmable Logic Devices	最大供电电压：	5.25 V
最小供电电压：	4.75 V	标称供电电压：	5 V
表面贴装：	NO	技术：	CMOS
温度等级：	COMMERCIAL EXTENDED	端子形式：	THROUGH-HOLE
端子节距：	2.54 mm	端子位置：	DUAL
处于峰值回流温度下的最长时间：	NOT SPECIFIED	宽度：	7.62 mm
Base Number Matches：	1

PLC42VA12N 数据手册

Philips Semiconductors Programmable Logic Devices

Product specification

CMOS programmable multi-function PLD

(42 × 105 × 12)

PLC42VA12

DESCRIPTION

FEATURES

PIN CONFIGURATIONS

The new PLC42VA12 CMOS PLD from

Philips Semiconductors exhibits a unique

combination of the two architectural concepts

that revolutionized the PLD marketplace.

• High-speed EPROM-based CMOS

Multi-Function PLD

FA and N Pack-

ages

– Super set of 22V10, 32VX10 and

20RA10 PAL ICs

I0/CLK

The Philips Semiconductors unique Output

Macro Cell (OMC) embodies all the

I9/OE

• Two fully programmable arrays eliminate

“P-term Depletion”

advantages and none of the disadvantages

associated with the “V” type Output Macro

Cell devices. This new design, combined with

added functionality of two programmable

arrays, represents a significant advancement

in the configurability and efficiency of

multi-function PLDs.

– Up to 64 P-terms per OR function

• Improved Output Macro Cell Structure

– Individually programmable as:

* Registered Output with feedback

* Registered Input

* Combinatorial I/O with Buried Register

* Dedicated I/O with feedback

* Dedicated Input (combinatorial)

The most significant improvement in the

Output Macro Cell structure is the

implementation of the register bypass

function. Any of the 10 J-K/D registers can be

individually bypassed, thus creating a

combinatorial I/O path from the AND array to

the output pin. Unlike other “V” type devices,

the register in the PLC42VA12 Macro Cell

remains fully functional as a buried register.

Both the combinatorial I/O and buried register

have separate input paths (from the AND

array). In most V-type architectures, the

configured as a combinatorial I/O. This

feature provides the capability to operate the

buried register independently from the

combinatorial I/O.

– Bypassed Registers are 100% functional

with separate input and feedback paths

GND 12

– Individual Output Enable control

functions

N = Plastic DIP (300mil-wide)

FA = Ceramic DIP with Quartz Window (300mil-wide)

* From pin or AND array

• Reprogrammable – 100% tested for

programmability

• Eleven clock sources

• Register Preload and Diagnostic Test Mode

A Package

Features

I0/

I2 I1 CLK N/C

M9 M8

• Security fuse

28 27 26

APPLICATIONS

The PLC42VA12 is an EPROM-based CMOS

device. Designs can be generated using

Philips Semiconductors SNAP PLD design

software packages or one of several other

commercially available JEDEC standard PLD

design software packages.

• Mealy or Moore State Machines

– Synchronous

N/C

22 N/C

– Asynchronous

• Multiple, independent State Machines

• 10-bit ripple cascade

• Sequence recognition

• Bus Protocol generation

• Industrial control

12 13 14 15 16 17 18

B0 B1 GND N/C I9/ M0 M1

A = Plastic Leaded Chip Carrier (450mil-square)

• A/D Scanning

ORDERING INFORMATION

DESCRIPTION

ORDER CODE

DRAWING NUMBER

24-Pin Ceramic Dual In-Line with window,

Reprogrammable (300mil-wide)

PLC42VA12FA

1478A

24-Pin Plastic Dual In-Line,

One Time Programmable (300mil-wide)

PLC42VA12N

PLC42VA12A

0410D

0401F

28-Pin Plastic Leaded Chip Carrier,

One Time Programmable (450mil-wide)

PAL is a registered trademark of Advanced Micro Devices, Inc.

October 22, 1993

853–1414 11164

12 3 4 5 6 7...20

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