5秒后页面跳转
捷配首页

Datasheet > 可编程逻辑 > 可编程逻辑器件> PLC42VA12A
PLC42VA12A PDF预览

PLC42VA12A

更新时间： 2024-11-10 22:12:51
品牌 Logo 应用领域
恩智浦 - NXP 可编程逻辑器件输入元件时钟
页数 文件大小 规格书
20页 437K
描述
CMOS programmable multi-function PLD 42 】 105 】 12

阅读下载

中文翻译

获取价格

PLC42VA12A 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：QLCC包装说明：QCCJ, LDCC28,.5SQ
针数：28Reach Compliance Code：unknown
HTS代码：8542.39.00.01风险等级：5.91
Is Samacsys：N其他特性：PROGRAMMABLE MULTI-FUNCTION PLD; 1 EXTERNAL CLOCK; SHARED INPUT/CLOCK; REGISTER PRELOAD
架构：PLS-TYPE最大时钟频率：14.9 MHz
JESD-30 代码：S-PQCC-J28长度：11.505 mm
湿度敏感等级：1专用输入次数：8
I/O 线路数量：12输入次数：42
输出次数：12产品条款数：105
端子数量：28最高工作温度：75 °C
最低工作温度：组织：8 DEDICATED INPUTS, 12 I/O
输出函数：MACROCELL封装主体材料：PLASTIC/EPOXY
封装代码：QCCJ封装等效代码：LDCC28,.5SQ
封装形状：SQUARE封装形式：CHIP CARRIER
峰值回流温度（摄氏度）：225电源：5 V
可编程逻辑类型：OT PLD传播延迟：55 ns
认证状态：Not Qualified座面最大高度：4.57 mm
子类别：Programmable Logic Devices最大供电电压：5.25 V
最小供电电压：4.75 V标称供电电压：5 V
表面贴装：YES技术：CMOS
温度等级：COMMERCIAL EXTENDED端子形式：J BEND
端子节距：1.27 mm端子位置：QUAD
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：11.505 mm
Base Number Matches：1

PLC42VA12A 数据手册

 浏览型号PLC42VA12A的Datasheet PDF文件第2页浏览型号PLC42VA12A的Datasheet PDF文件第3页浏览型号PLC42VA12A的Datasheet PDF文件第4页浏览型号PLC42VA12A的Datasheet PDF文件第5页浏览型号PLC42VA12A的Datasheet PDF文件第6页浏览型号PLC42VA12A的Datasheet PDF文件第7页 
Philips Semiconductors Programmable Logic Devices  
Product specification  
CMOS programmable multi-function PLD  
(42 × 105 × 12)  
PLC42VA12  
DESCRIPTION  
FEATURES  
PIN CONFIGURATIONS  
The new PLC42VA12 CMOS PLD from  
Philips Semiconductors exhibits a unique  
combination of the two architectural concepts  
that revolutionized the PLD marketplace.  
• High-speed EPROM-based CMOS  
Multi-Function PLD  
FA and N Pack-  
ages  
– Super set of 22V10, 32VX10 and  
20RA10 PAL ICs  
1
2
24  
V
I0/CLK  
I1  
CC  
The Philips Semiconductors unique Output  
Macro Cell (OMC) embodies all the  
23  
22  
21  
20  
19  
18  
17  
16  
15  
14  
13  
M9  
M8  
M7  
M6  
M5  
M4  
M3  
M2  
M1  
M0  
I9/OE  
• Two fully programmable arrays eliminate  
“P-term Depletion”  
3
I2  
advantages and none of the disadvantages  
associated with the “V” type Output Macro  
Cell devices. This new design, combined with  
added functionality of two programmable  
arrays, represents a significant advancement  
in the configurability and efficiency of  
multi-function PLDs.  
– Up to 64 P-terms per OR function  
4
I3  
5
I4  
• Improved Output Macro Cell Structure  
– Individually programmable as:  
* Registered Output with feedback  
* Registered Input  
6
I5  
7
I6  
8
I7  
* Combinatorial I/O with Buried Register  
* Dedicated I/O with feedback  
* Dedicated Input (combinatorial)  
9
I8  
The most significant improvement in the  
Output Macro Cell structure is the  
10  
11  
B0  
B1  
implementation of the register bypass  
function. Any of the 10 J-K/D registers can be  
individually bypassed, thus creating a  
combinatorial I/O path from the AND array to  
the output pin. Unlike other “V” type devices,  
the register in the PLC42VA12 Macro Cell  
remains fully functional as a buried register.  
Both the combinatorial I/O and buried register  
have separate input paths (from the AND  
array). In most V-type architectures, the  
register is lost as a resource when the cell is  
configured as a combinatorial I/O. This  
feature provides the capability to operate the  
buried register independently from the  
combinatorial I/O.  
– Bypassed Registers are 100% functional  
with separate input and feedback paths  
GND 12  
– Individual Output Enable control  
functions  
N = Plastic DIP (300mil-wide)  
FA = Ceramic DIP with Quartz Window (300mil-wide)  
* From pin or AND array  
• Reprogrammable – 100% tested for  
programmability  
• Eleven clock sources  
• Register Preload and Diagnostic Test Mode  
A Package  
Features  
I0/  
I2 I1 CLK N/C  
M9 M8  
V
• Security fuse  
CC  
28 27 26  
4
3
2
1
5
6
25  
24  
23  
I3  
I4  
M7  
M6  
M5  
APPLICATIONS  
The PLC42VA12 is an EPROM-based CMOS  
device. Designs can be generated using  
Philips Semiconductors SNAP PLD design  
software packages or one of several other  
commercially available JEDEC standard PLD  
design software packages.  
• Mealy or Moore State Machines  
– Synchronous  
7
I5  
N/C  
8
22 N/C  
– Asynchronous  
9
21  
20  
19  
I6  
I7  
I8  
M4  
M3  
M2  
• Multiple, independent State Machines  
• 10-bit ripple cascade  
• Sequence recognition  
• Bus Protocol generation  
• Industrial control  
10  
11  
12 13 14 15 16 17 18  
B0 B1 GND N/C I9/ M0 M1  
OE  
A = Plastic Leaded Chip Carrier (450mil-square)  
• A/D Scanning  
ORDERING INFORMATION  
DESCRIPTION  
ORDER CODE  
DRAWING NUMBER  
24-Pin Ceramic Dual In-Line with window,  
Reprogrammable (300mil-wide)  
PLC42VA12FA  
1478A  
24-Pin Plastic Dual In-Line,  
One Time Programmable (300mil-wide)  
PLC42VA12N  
PLC42VA12A  
0410D  
0401F  
28-Pin Plastic Leaded Chip Carrier,  
One Time Programmable (450mil-wide)  
PAL is a registered trademark of Advanced Micro Devices, Inc.  
73  
October 22, 1993  
853–1414 11164  
1234567...20

中文翻译

下载PDF

与PLC42VA12A相关器件

型号 品牌 获取价格 描述 数据表
PLC42VA12FA NXP

获取价格

 		CMOS programmable multi-function PLD 42 】 105
PLC42VA12IA ETC

获取价格

 		UV-Erasable/OTP PLD
PLC42VA12IFA ETC

获取价格

 		UV-Erasable/OTP PLD
PLC42VA12IN ETC

获取价格

 		UV-Erasable/OTP PLD
PLC42VA12N NXP

获取价格

 		CMOS programmable multi-function PLD 42 】 105
PLC-45 MEANWELL

获取价格

 		45W Single Output LED Power Supply
PLC-45_12 MEANWELL

获取价格

 		45W Single Output LED Power Supply
PLC4510 LSTD

获取价格

 		Heavy-duty construction
PLC4510N LSTD

获取价格

 		Heavy-duty construction
PLC-45-12 MEANWELL

获取价格

 		45W Single Output LED Power Supply

与PLC42VA12A相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证