Philips Semiconductors Programmable Logic Devices
Product specification
CMOS programmable multi-function PLD
(42 × 105 × 12)
PLC42VA12
DESCRIPTION
FEATURES
PIN CONFIGURATIONS
The new PLC42VA12 CMOS PLD from
Philips Semiconductors exhibits a unique
combination of the two architectural concepts
that revolutionized the PLD marketplace.
• High-speed EPROM-based CMOS
Multi-Function PLD
FA and N Pack-
ages
– Super set of 22V10, 32VX10 and
20RA10 PAL ICs
1
2
24
V
I0/CLK
I1
CC
The Philips Semiconductors unique Output
Macro Cell (OMC) embodies all the
23
22
21
20
19
18
17
16
15
14
13
M9
M8
M7
M6
M5
M4
M3
M2
M1
M0
I9/OE
• Two fully programmable arrays eliminate
“P-term Depletion”
3
I2
advantages and none of the disadvantages
associated with the “V” type Output Macro
Cell devices. This new design, combined with
added functionality of two programmable
arrays, represents a significant advancement
in the configurability and efficiency of
multi-function PLDs.
– Up to 64 P-terms per OR function
4
I3
5
I4
• Improved Output Macro Cell Structure
– Individually programmable as:
* Registered Output with feedback
* Registered Input
6
I5
7
I6
8
I7
* Combinatorial I/O with Buried Register
* Dedicated I/O with feedback
* Dedicated Input (combinatorial)
9
I8
The most significant improvement in the
Output Macro Cell structure is the
10
11
B0
B1
implementation of the register bypass
function. Any of the 10 J-K/D registers can be
individually bypassed, thus creating a
combinatorial I/O path from the AND array to
the output pin. Unlike other “V” type devices,
the register in the PLC42VA12 Macro Cell
remains fully functional as a buried register.
Both the combinatorial I/O and buried register
have separate input paths (from the AND
array). In most V-type architectures, the
register is lost as a resource when the cell is
configured as a combinatorial I/O. This
feature provides the capability to operate the
buried register independently from the
combinatorial I/O.
– Bypassed Registers are 100% functional
with separate input and feedback paths
GND 12
– Individual Output Enable control
functions
N = Plastic DIP (300mil-wide)
FA = Ceramic DIP with Quartz Window (300mil-wide)
* From pin or AND array
• Reprogrammable – 100% tested for
programmability
• Eleven clock sources
• Register Preload and Diagnostic Test Mode
A Package
Features
I0/
I2 I1 CLK N/C
M9 M8
V
• Security fuse
CC
28 27 26
4
3
2
1
5
6
25
24
23
I3
I4
M7
M6
M5
APPLICATIONS
The PLC42VA12 is an EPROM-based CMOS
device. Designs can be generated using
Philips Semiconductors SNAP PLD design
software packages or one of several other
commercially available JEDEC standard PLD
design software packages.
• Mealy or Moore State Machines
– Synchronous
7
I5
N/C
8
22 N/C
– Asynchronous
9
21
20
19
I6
I7
I8
M4
M3
M2
• Multiple, independent State Machines
• 10-bit ripple cascade
• Sequence recognition
• Bus Protocol generation
• Industrial control
10
11
12 13 14 15 16 17 18
B0 B1 GND N/C I9/ M0 M1
OE
A = Plastic Leaded Chip Carrier (450mil-square)
• A/D Scanning
ORDERING INFORMATION
DESCRIPTION
ORDER CODE
DRAWING NUMBER
24-Pin Ceramic Dual In-Line with window,
Reprogrammable (300mil-wide)
PLC42VA12FA
1478A
24-Pin Plastic Dual In-Line,
One Time Programmable (300mil-wide)
PLC42VA12N
PLC42VA12A
0410D
0401F
28-Pin Plastic Leaded Chip Carrier,
One Time Programmable (450mil-wide)
PAL is a registered trademark of Advanced Micro Devices, Inc.
73
October 22, 1993
853–1414 11164
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