PL680-39

更新时间： 2024-02-02 18:19:25

品牌	Logo	应用领域
PLL		石英晶振
页数	文件大小	规格书
10页	300K
描述
38-640MHz Low Phase Noise XO

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技术参数
数据手册

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PL680-39 技术参数

生命周期：	Obsolete	Reach Compliance Code：	unknown
风险等级：	5.84

PL680-39 数据手册

(Preliminary) PL680-37/38/39

38-640MHz Low Phase Noise XO

FEATURES

PACKAGE PIN ASSIGNMENT

•

Less than 0.4ps RMS (12KHz-20MHz) phase

jitter for all frequencies.

Less than 25ps peak to peak jitter for all

frequencies.

Low phase noise output (@ 1MHz frequency

offset

VDDANA

XIN

SEL0^

SEL1^

XOUT

SEL2^

OE_CTRL

DNC

GNDBUF

QBAR

∗

-144dBc/Hz for 106.25MHz

-144dBc/Hz for 156.25MHz

-144dBc/Hz for 212.5MHz

-140dBc/Hz for 312.5MHz,

-131dBC/Hz for 622.08MHz

VDDBUF

GNDBUF

GNDANA

•

19MHz-40MHz crystal input.

38MHz-640MHz output.

Available in PECL, LVDS, or CMOS outputs.

Output Enable selector.

2.5V & 3.3V operation.

Available in 3x3 QFN or 16-pin TSSOP

packages.

16-pin TSSOP

12 11 10

XOUT

SEL2^

GNDBUF

QBAR

VDDBUF

DESCRIPTION

PL680-3X

OE_CTRL

DNC

The PL680-3X is a monolithic low jitter and low

phase noise high performance clock, capable of

maintaining 0.4ps RMS phase jitter and CMOS,

LVDS or PECL outputs, covering a wide frequency

output range up to 640MHz. It allows high

performance and high frequency output, using a low

cost fundamental crystal of between 19-40MHz..

The frequency selector pads of PL680-3X enable

output frequencies of (2, 4, 8, or 16) * F_XIN. The

PL680-3X is designed to address the demanding

requirements of high performance applications such

Fiber Channel, serial ATA, Ethernet, SAN, etc.

3x3 QFN

Note1: QBAR is used for single ended CMOS output.

Note2: ^ Denotes internal pull up resistor.

BLOCK DIAGRAM

VCO

Divider

Charge

Output

QBAR

VCO

(F_XiNx16)

Pump

XIN

Phase

Detector

XTAL

OSC

Divider

Loop

(1,2,4,8)

XOUT

Filter

Performance Tuner

47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 11/28/05 Page 1

12 3 4 5 6 7...10

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