Datasheet > PL680-38OI-R

PL680-38OI-R

更新时间： 2024-01-30 17:55:19

品牌	Logo	应用领域
PLL		/
页数	文件大小	规格书
10页	239K
描述
Oscillator

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中文翻译

获取价格

技术参数
数据手册

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PL680-38OI-R 技术参数

生命周期：	Obsolete	Reach Compliance Code：	unknown
风险等级：	5.84	Base Number Matches：	1

PL680-38OI-R 数据手册

PL680-37/38/39

38-640MHz Low Phase Noise XO

FEATURES

PACKAGE PIN ASSIGNMENT



Typical 0.4ps RMS (12kHz to 20MHz) phase jitter.

Typical 25ps peak to peak period jitter.

Low phase noise output (@ 1MHz offset)

VDDANA

XIN

SEL0^

SEL1^

-144dBc/Hz for 156.25MHz

-144dBc/Hz for 212.5MHz

-131dBc/Hz for 622.08MHz

XOUT

SEL2^

OE_CTRL

DNC

GNDBUF

QBAR



Fundamental Crystal Input Frequency:

VDDBUF

19MHz to 40MHz (3.3V)

19MHz to 28.125MHz (2.5V)

Output Frequency:

GNDBUF

GNDANA

38MHz to 640MHz (3.3V)

38MHz to 450MHz (2.5V)



Available in LVPECL, LVDS, or LVCMOS outputs.

Output Enable selector.

2.5V to 3.3V, ±10% operation.

16-pin TSSOP

Available in 3x3 QFN or 16-pin TSSOP packages.

DESCRIPTION

12 11 10

The PL680-3X is a monolithic low jitter and low phase

noise high performance clock, capable of producing

0.4ps RMS phase jitter and LVCMOS, LVDS or LVPECL

outputs, covering a wide frequency output range up to

640MHz. It allows high performance and high frequency

output, using a low cost fundamental crystal of 19MHz to

40MHz.

XOUT

SEL2^

GNDBUF

QBAR

VDDBUF

OE_CTRL

DNC

The frequency selector pads of PL680-3X enable output

frequencies of (2, 4, 8, or 16) * F_XIN. The PL680-3X is

designed to address the demanding requirements of high

performance applications such Fiber Channel, serial ATA,

Ethernet, SAN, etc.

3x3 QFN

Note1: QBAR is used for single ended LVCMOS output.

Note2: ^ Denotes 60kΩ internal pull up resistor.

BLOCK DIAGRAM

47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 8/19/09 Page 1

12 3 4 5 6 7...10

中文翻译

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