Datasheet > PJSR70TB4

PJSR70TB4

更新时间： 2024-02-14 08:45:19

品牌	Logo	应用领域
强茂 - PANJIT		二极管光电二极管局域网
页数	文件大小	规格书
3页	95K
描述
Very Low Capacitance Diode Array

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技术参数
数据手册

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PJSR70TB4 技术参数

生命周期：	Active	包装说明：	R-PDSO-F4
针数：	4	Reach Compliance Code：	compliant
ECCN代码：	EAR99	HTS代码：	8541.10.00.50
风险等级：	5.78	Is Samacsys：	N
最小击穿电压：	85 V	配置：	COMPLEX
二极管元件材料：	SILICON	二极管类型：	TRANS VOLTAGE SUPPRESSOR DIODE
JESD-30 代码：	R-PDSO-F4	JESD-609代码：	e3
元件数量：	4	端子数量：	4
最高工作温度：	125 °C	最低工作温度：	-55 °C
封装主体材料：	PLASTIC/EPOXY	封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE	极性：	UNIDIRECTIONAL
认证状态：	Not Qualified	最大重复峰值反向电压：	70 V
表面贴装：	YES	技术：	AVALANCHE
端子面层：	MATTE TIN	端子形式：	FLAT
端子位置：	DUAL	Base Number Matches：	1

PJSR70TB4 数据手册

PJSR70TB4

Very Low Capacitance Diode Array

This diode array is configured to protect up to two high speed data

transmission lines, used in Low Voltage Differential Signal (LVDS) ports.

Acting as a line terminator, minimizes overshoot and undershoot

conditions

SOT543 Package

due to bus impedance as well as protect against over-voltage events as

electrostatic discharges. This configuration comes in the new SOT543

package, offering a significative printed circuit board space savings

compared to the SOT143.

SPECIFICATION FEATURES

Maximum Capacitance of 1.0pF at 0Vdc 1MHz Line-to-Ground

Maximum Leakage Current of 1.0µA @ VRWM

New SMT Package SOT543

Line1

+VREF

IEC61000-4-2 Full Compliance; 15kV Air, 8kV Contact*

100% Tin Matte finish (LEAD-FREE PRODUCT)

APPLICATIONS

USB 2.0 and Firewire Port Protection

Line2

Gnd

HDMI Version 1.3

DVI

Tj = 25°C Unless otherwise noted

MAXIMUM RATINGS

Rating

Symbol

Value

Units

Peak Pulse Current (8/20µs Waveform)

Rectifier Repetitive Peak Reverse Voltage

PPM

RRM

-55 to +125

-55 to +150

260

°C

Operating Junction Temperature Range

Storage Temperature Range

stg

Soldering Temperature, t max = 10s

Note: ESD Testing requires to connect a TVS between +VREF and GND, if there is no +VREF Bias connected.

2/18/2009

www.panjit.com

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