PI90LV14

更新时间： 2024-09-28 21:54:03

品牌	Logo	应用领域
百利通 - PERICOM		时钟
页数	文件大小	规格书
6页	123K
描述
1:5 Clock Distribution

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中文翻译

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数据手册

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PI90LV14 数据手册

PI90LV14/PI90LVT14

1:5 Clock Distribution

Features

Description

• Meets and Exceeds the Requirements of ANSI

TIA/EIA-644-1995

ThePI90LV14implementslowvoltagedifferentialsignaling(LVDS)

to achieve clocking rates as high as 320MHz with low skew.

• Designed for clocking rates up to 320MHz

• Operates from a single 3.3V Supply

• LowVoltageDifferentialSignaling(LVDS)withOutput

Voltages of ±350mV into a 100Ωload

• Choice between LVDS or TTL clock input

• Synchronous Enable/Disable

The PI90LV14 is a low-skew 1:5 clock distribution chip which

incorporates multiplexed clock inputs to allow for distribution of a

lower-speed, single-ended clock or a high-speed system clock.

When LOWthe SEL pin will select the differential clock input.

The common enable (EN) is synchronous so that the outputs will

only be enabled/disabled when they are already in the LOW state.

This avoids any chance of generating a runt clock pulse when the

device is enabled/disabled as can happen with an asynchronous

control.Becausetheinternalflip-flopisclockedonthefallingedge

oftheinputclock, allassociatedspecificationlimitsarereferenced

to the negative edge of the clock input.

• Clock outputs default LOW when inputs open

• Multiplexedclockinput

- Internal 300kΩpullup resistor on input pins

-CLKandCLKhave110Ωinternaltermination(PI90LVT14)

• 50ps Output-to-Output Skew

• 475ps typical propagation delay

• Bus Pins are high impedance when disabled or with

The intended application of these devices and signaling technique

is for high-speed clock distribution between boards.

less than 1.5V

• TTL inputs are 5V Tolerant

• Power Dissipation at 400Mbits/s of 150mW

• FunctioncompatibletoMotorola(PECL)

MC100EL14andMicrel/Synergy(PECL)

SY100EL14V

PI90LV14 Block Diagram

• >9kVESDProtection

CLK1_OUT+

• 20-pinTSSOP(L)andQSOP(Q)packages

CLK1_OUT–

Pin Descriptions

CLK, CLK

SCLK

Funtion

CLK2_OUT+

CLK2_OUT–

Differential Clock Outputs

LVTTL Clock Input

Synchronous Enable

Clock Select Input

GND

CLK3_OUT+

CLK3_OUT–

SCLK

CLK

SEL

Ω

CLK1-5_OUT±

Differential Clock Inputs

Function Table

CLK

CLK4_OUT+

CLK4_OUT–

CLK

SCLK

SEL

EN*

CLKOUT+

GND

SEL

CLK5_OUT+

CLK5_OUT–

↓

GND

↓

* On next negative transition of CLK, or SCLK

PS8538

04/25/01

12 3 4 5 6

中文翻译

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与PI90LV14相关器件

型号	品牌	获取价格	描述	数据表
PI90LV14L	PERICOM	获取价格	1:5 Clock Distribution
PI90LV14LE	PERICOM	获取价格	Low Skew Clock Driver, 90LV Series, 5 True Output(s), 0 Inverted Output(s), PDSO20, 0.173
PI90LV14LEX	PERICOM	获取价格	Low Skew Clock Driver, 90LV Series, 5 True Output(s), 0 Inverted Output(s), PDSO20, 0.173
PI90LV14LX	PERICOM	获取价格	Low Skew Clock Driver, 90LV Series, 5 True Output(s), 0 Inverted Output(s), PDSO20, 0.173
PI90LV14Q	PERICOM	获取价格	1:5 Clock Distribution
PI90LV14QE	PERICOM	获取价格	Low Skew Clock Driver, 90LV Series, 5 True Output(s), 0 Inverted Output(s), PDSO20, 0.150
PI90LV14QX	PERICOM	获取价格	Low Skew Clock Driver, 90LV Series, 5 True Output(s), 0 Inverted Output(s), PDSO20, 0.150
PI90LV179	PERICOM	获取价格	3.3V LVDS High-Speed Differential Line Drivers and Receivers
PI90LV179_15	PERICOM	获取价格	3.3V LVDS High-Speed Differential Line Driver and Receiver
PI90LV179U	PERICOM	获取价格	3.3V LVDS High-Speed Differential Line Drivers and Receivers

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