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PI74SSTV16859FZBE

更新时间： 2024-09-15 20:04:31
品牌 Logo 应用领域
百利通 - PERICOM 逻辑集成电路触发器电视
页数 文件大小 规格书
7页 188K
描述
D Flip-Flop, SSTV Series, 1-Func, Positive Edge Triggered, 13-Bit, True Output, CMOS, PQCC56, PLASTIC, MO-220VLLD-2, QFN-56

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PI74SSTV16859FZBE 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：QFN
包装说明：PLASTIC, MO-220VLLD-2, QFN-56针数：56
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：5.26
系列：SSTVJESD-30 代码：S-PQCC-N56
长度：8 mm逻辑集成电路类型：D FLIP-FLOP
位数：13功能数量：1
端子数量：56最高工作温度：70 °C
最低工作温度：输出极性：TRUE
封装主体材料：PLASTIC/EPOXY封装代码：HVQCCN
封装形状：SQUARE封装形式：CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度（摄氏度）：NOT SPECIFIED传播延迟（tpd）：2.6 ns
认证状态：Not Qualified座面最大高度：0.84 mm
最大供电电压 (Vsup)：2.7 V最小供电电压 (Vsup)：2.3 V
标称供电电压 (Vsup)：2.5 V表面贴装：YES
技术：CMOS温度等级：COMMERCIAL
端子形式：NO LEAD端子节距：0.5 mm
端子位置：QUAD处于峰值回流温度下的最长时间：NOT SPECIFIED
触发器类型：POSITIVE EDGE宽度：8 mm
最小 fmax：200 MHzBase Number Matches：1

PI74SSTV16859FZBE 数据手册

 浏览型号PI74SSTV16859FZBE的Datasheet PDF文件第2页浏览型号PI74SSTV16859FZBE的Datasheet PDF文件第3页浏览型号PI74SSTV16859FZBE的Datasheet PDF文件第4页浏览型号PI74SSTV16859FZBE的Datasheet PDF文件第5页浏览型号PI74SSTV16859FZBE的Datasheet PDF文件第6页浏览型号PI74SSTV16859FZBE的Datasheet PDF文件第7页 
TARGET SPECIFICATION  
PI74SSTV16859F  
13-Bit to 26-Bit Registered Buffer  
ProductFeatures  
ProductDescription  
PericomSemiconductor’sPI74SSTV16859Flogiccircuitisproduced  
using the Company’s advanced sub-micron CMOS technology,  
achieving industry leading speed.  
All inputs are compatible with the JEDEC standard for SSTL_2,  
excepttheLVCMOSreset(RESET)input.AlloutputsareSSTL_2,  
ClassIIcompatible.  
Thedeviceoperatesfromadifferentialclock(CLKandCLK).Data  
registeredatthecrossingofCLKgoingHIGH,andCLKgoingLOW.  
ThePI74SSTV16859Fsupportslow-powerstandbyoperation.When  
RESET is LOW, the differential input receivers are disabled, and  
undriven (floating) data, clock and reference voltage (VREF) inputs  
areallowed.Inaddition,whenRESETisLOW,allregistersarereset,  
and all outputs are forced LOW. The LVCMOS RESET input must  
always be held at a valid logic HIGH or LOW level.  
To ensure defined outputs from the register before a stable clock  
has been supplied, RESET must be held in the LOW state during  
power up.  
IntheDDRDIMMapplication,RESETisspecifiedtobecompletely  
asynchronous with respect to CLK and CLK. Therefore, no timing  
relationship can be guaranteed between the two. When entering  
RESET, the register will be cleared and the outputs will be driven  
LOW quickly, relative to the time to disable the differential input  
receivers, thus ensuring no glitches on the output. However, when  
comingoutof RESET,theregisterwillbecomeactivequickly,relative  
to the time to enable the differential input receivers. When the data  
inputs are LOW, and the clock is stable, during the time from the  
LOW-to-HIGH transition of RESET until the input receivers  
are fully enabled, the design must ensure that the outputs will  
remainLOW.  
• PI74SSTV16859Fisdesignedforlow-voltageoperation,  
V
DD  
=V  
=2.3Vto2.7V  
DDQ  
• Supports SSTL_2 Class II specifications on outputs  
• All InputsareSSTL_2Compatible,exceptRESET  
whichisLVCMOS.  
• Designed for DDR Memory  
• Flow-Through Architecture  
• Packages:  
64-pin,240-milwideplasticTSSOP(A)  
56-pin, Plastic Very Thin Fine Pitch Quad Flat  
No Lead QFN (ZB)  
Logic Block Diagram - TSSOP  
48  
CLK  
49  
CLK  
16  
51  
Q1A  
Q1B  
RESET  
R
CLK  
35  
45  
32  
D1  
D
V
REF  
TO 12 OTHER CHANNELS  
Logic Block Diagram - QFN  
35  
CLK  
36  
CLK  
7
38  
Q1A  
Q1B  
RESET  
R
D
CLK  
24  
D1  
22  
32  
V
Pericom’s PI74SSTV16859F is characterized for operation from  
0°Cto70°C.  
REF  
TruthTable(1)  
TO 12 OTHER CHANNELS  
Inputs  
Outputs  
Q
ProductPinDescription  
RESET  
CLK  
X or  
CLK  
X or  
D
Pin Name  
RESET  
CLK  
CLK  
D
Description  
X or  
Floating  
L
L
Reset (Active Low) LVCMOS  
Clock Input, Positive Differential Input  
Clock Input, Negative Differential Input  
Data Input, D1-D13  
Floating  
Floating  
H
Η
H
↑
↓
H
L
X
H
L
Qo(2)  
↑
↓
L or H  
L or H  
Q
Data Output, Q1-Q13  
Notes:  
GND  
VDD  
VDDQ  
VREF  
Ground  
1.  
H
L
↑
↓
X
= HighSignalLevel  
= LowSignalLevel  
2. Output level before the  
indicated steady state  
input conditions were  
established.  
Core Supply Voltage, 2.5V Nominal  
Output Supply Voltage, 2.5V Nominal  
Input Reference Voltage, 1.25V Nominal  
= Transition LOW-to-HIGH  
= Transition HIGH-to-LOW  
= Irrelevant or floating  
1
P-0  
09/17/02  
1234567

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