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PI74LPT16543CAX

更新时间： 2024-11-25 13:12:23
品牌 Logo 应用领域
百利通 - PERICOM /
页数 文件大小 规格书
5页 60K
描述
Registered Bus Transceiver, LPT Series, 2-Func, 8-Bit, True Output, CMOS, PDSO56, 0.240 INCH, 1.10 MM HEIGHT, 0.50 MM PITCH, PLASTIC, TSSOP-56

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PI74LPT16543CAX 技术参数

生命周期：Obsolete零件包装代码：TSSOP
包装说明：TSSOP,针数：56
Reach Compliance Code：unknownECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：5.28
Is Samacsys：N其他特性：INDEPENDENT OUTPUT ENABLE FOR EACH DIRECTION
系列：LPTJESD-30 代码：R-PDSO-G56
JESD-609代码：e0长度：14 mm
负载电容（CL）：50 pF逻辑集成电路类型：REGISTERED BUS TRANSCEIVER
位数：8功能数量：2
端口数量：2端子数量：56
最高工作温度：85 °C最低工作温度：-40 °C
输出特性：3-STATE输出极性：TRUE
封装主体材料：PLASTIC/EPOXY封装代码：TSSOP
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
传播延迟（tpd）：8.4 ns认证状态：Not Qualified
座面最大高度：1.2 mm最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：2.7 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：TIN LEAD
端子形式：GULL WING端子节距：0.5 mm
端子位置：DUAL宽度：6.1 mm
Base Number Matches：1

PI74LPT16543CAX 数据手册

 浏览型号PI74LPT16543CAX的Datasheet PDF文件第2页浏览型号PI74LPT16543CAX的Datasheet PDF文件第3页浏览型号PI74LPT16543CAX的Datasheet PDF文件第4页浏览型号PI74LPT16543CAX的Datasheet PDF文件第5页 
PI74LPT16543  
1
2
Fast CMOS 16-Bit Latched Transceivers  
Product Features  
• CompatiblewithLCX™andLVT™familiesofproducts  
Product Description  
Pericom Semiconductor’s PI74LPT series of logic circuits are pro-  
duced in the Company’s advanced 0.6 micron CMOS technology,  
achieving industry leading speed grades.  
• Supports 5V Tolerant Mixed Signal Mode Operation  
– Input can be 3V or 5V  
3
– Output can be 3V or connected to 5V bus  
The PI74LPT16543 is 16-bit latched transceivers organized with  
two sets of eight D-type latches with separate input and output  
controls for each set. For data flow from A to B, for example, the A-  
to-B Enable (xCEAB) input must be LOW in order to enter data  
from xAx or to take data from xBx, as indicated in the Truth Table.  
With xCEAB LOW, a LOW signal makes the A-to-B latches  
transparent; a subsequent LOW-to-HIGH transition of the xLEAB  
signal puts the A latches in the storage mode and their outputs no  
longer change the A inputs. With xCEAB and xOEAB both LOW,  
the 3-state B output buffers are active and reflect the data present at  
the output of the A latches. Control of data from B to A is similar,  
but uses the xCEAB, xLEAB, and xOEAB inputs.  
• Advanced Low Power CMOS Operation  
• Excellent output drive capability:  
Balanced drives (24 mA sink and source)  
4
5
• Pin compatible with industry standard double-density  
pinouts  
• Low ground bounce outputs  
• Hysteresis on all inputs  
• Industrial operating temperature range: –40°C to +85°C  
• Multiple center pins and distributed Vcc/GND pins  
minimize switching noise  
6
ThePI74LPT16543canbedrivenfromeither3.3Vor5.0Vdevices  
allowing this device to be used as a translator in a mixed 3.3/5.0V  
system.  
• Packages available:  
–56-pin240milwideplasticTSSOP(A)  
–56-pin300milwideplasticSSOP(V)  
7
8
Logic Block Diagram  
1OEBA  
2OEBA  
9
1CEBA  
2CEBA  
10  
11  
12  
13  
14  
15  
1
LEBA  
2
LEBA  
1OEAB  
2OEAB  
1CEAB  
2CEAB  
1LEAB  
2LEAB  
C
D
C
D
1
B0  
2B0  
1
A0  
2A0  
C
D
C
D
TO 7 OTHER CHANNELS  
TO 7 OTHER CHANNELS  
PS2072A 01/16/97  
1
12345

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