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PI74FCT162952ATV

更新时间: 2024-01-08 16:30:33
品牌 Logo 应用领域
其他 - ETC 总线收发器触发器逻辑集成电路光电二极管输出元件
页数 文件大小 规格书
7页 237K
描述
Dual 8-bit Bus Transceiver

PI74FCT162952ATV 数据手册

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PI74FCT16952T  
PI74FCT162952T
PI74FCT162H952T  
16-Bit Registered Transceivers  
ProductFeatures:  
CommonFeatures:  
Product Description:  
Pericom Semiconductor’s PI74FCT series of logic circuits are pro-  
duced in the Company’s advanced 0.6 micron CMOS technology,  
achieving industry leading speed grades.  
• PI74FCT16952T,PI74FCT162952T,andPI74FCT2H952T  
are high-speed,  
low power devices with high current drive  
• VCC =5V±10%  
ThePI74FCT16952T,PI74FCT162952T,and PI74FCT162H952T  
are 16-bit registered transceivers organized with two sets of eight  
D-type latches with separate input and output controls for each set.  
For data flow from A to B, for example, the A-to-B Enable  
(xCEAB) input must be LOW in order to enter data from xAx. The  
data present on the A port will be clocked on the B register when  
xCLKAB toggles from LOW-to-HIGH. The xOEAB control  
performs the output enable function on the B port. Control of data  
from B to A is similar, but uses the xCEBA, xCLKBA, and xOEBA  
inputs. By connecting the control pins of the two independent  
transceivers together, a full 16-bit operation can be achieved. The  
output buffers are designed with a Power-Off disable allowing  
“live insertion” of boards when used as backplane drivers.  
• Hysteresis on all inputs  
• Packagesavailable:  
– 56-pin240milwideplasticTSSOP(A)  
– 56-pin300milwide plasticSSOP(V)  
PI74FCT16952TFeatures:  
• High output drive: IOH = –32 mA; IOL = 64 mA  
• Power off disable outputs permit “live insertion”  
• Typical VOLP (Output Ground Bounce) < 1.0V  
atVCC =5V,TA =25°C  
PI74FCT162952TFeatures:  
The PI74FCT16952T output buffers are designed with a Power-  
Off disable function allowing “live insertion” of boards when used  
as backplane drivers.  
• Balanced output drivers: ±24 mA  
• Reduced system switching noise  
The PI74FCT162952T has ±24 mA balanced output drivers. It is  
designed with current limiting resistors at its outputs to control the  
output edge rate resulting in lower ground bounce and undershoot.  
This eliminates the need for external terminating resistors for most  
interface applications.  
• Typical VOLP (Output Ground Bounce) < 0.6V  
atVCC =5V,TA =25°C  
PI74FCT162H952TFeatures:  
• Bus Hold retains last active bus state during 3-state  
• Eliminates the need for external pull-up resistors  
The PI74FCT162H952T has “Bus Hold” which retains the input’s  
last state whenever the input goes to high-impedance preventing  
“floating”inputsandeliminatingtheneedforpull-up/downresistors.  
Logic Block Diagram  
1OEBA  
2OEBA  
1CEBA  
2CEBA  
1
CLKBA  
OEAB  
CEAB  
2
CLKBA  
OEAB  
CEAB  
1
2
1
2
1
CLKAB  
2CLKAB  
C
C
1
A
0
2A0  
1B  
0
2B0  
D
D
C
C
D
D
TO 7 OTHER CHANNELS  
TO 7 OTHER CHANNELS  
PS2042A 03/11/96  
1

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