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PI74FCT162500DTV PDF预览

PI74FCT162500DTV

更新时间: 2024-10-27 23:27:39
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页数 文件大小 规格书
6页 255K
描述
18-Bit Bus Transceiver

PI74FCT162500DTV 数据手册

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PI74FCT16500T
PI74FCT162500T  
Fast CMOS 18-Bit  
Registered Transceivers  
Product Description:  
Pericom Semiconductor’s PI74FCT series of logic circuits are pro-  
duced in the Company’s advanced 0.8 micron CMOS technology,  
achieving industry leading speed grades.  
ProductFeatures:  
CommonFeatures:5  
• PI74FCT16500TandPI74FCT162500Tarehigh-speed,  
low power devices with high current drive.  
ThePI74FCT16500TandPI74FCT162500Tare18-bit registeredbus  
transceivers designed with D-type latches and flip-flops to allow  
data flow in transparent, latched, and clocked modes. The Output  
Enable (OEAB and OEBA), Latch Enable (LEAB and LEBA) and  
Clock (CLKAB and CLKBA) inputs control the data flow in each  
direction. When LEAB is HIGH, the device operates in transparent  
modeforA-to-Bdataflow. WhenLEABisLOW,theAdataislatched  
if CLKAB is held at a HIGH or LOW logic level. The A bus data is  
stored in the latch/flip-flop on the HIGH-to-LOW transition of  
CLKAB, if LEAB is LOW. OEAB performs the output enable  
functionontheBport. DataflowfromBporttoAportissimilarusing  
OEBA, LEBA and CLKBA. These high-speed, low power devices  
offer a flow-through organization for ease of board layout.  
• VCC =5V±10%  
• Hysteresis on all inputs  
• Packagesavailable:  
–56-pin240milwideplasticTSSOP(A)  
–56-pin300milwideplasticSSOP(V)  
PI74FCT16500TFeatures:  
• High output drive: IOH = –32 mA; IOL = 64 mA  
• Power off disable outputs permit “live insertion”  
• Typical VOLP (Output Ground Bounce) < 1.0V  
atVCC =5V,TA =25°C  
The PI74FCT16500T output buffers are designed with a Power-Off  
disable allowing “live insertion” of boards when used as backplane  
drivers.  
PI74FCT162500TFeatures:  
• Balanced output drivers: ±24 mA  
• Reduced system switching noise  
The PI74FCT162500T has ±24 mA balanced output drivers. It is  
designed with current limiting resistors at its outputs to control the  
output edge rate resulting in lower ground bounce and undershoot.  
This eliminates the need for external terminating resistors for most  
interface applications.  
• Typical VOLP (Output Ground Bounce) < 0.6V  
atVCC =5V,TA =25°C  
Logic Block Diagram  
OEAB  
CLKBA  
LEBA  
OEBA  
CLKAB  
LEAB  
C
D
C
B
1
A
1
D
C
D
C
D
TO 17 OTHER CHANNELS  
PS2077A 01/15/95  
1

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