PI74FCT16P37I37/146F23C73T/11662H373733TT
16-BIT TRANSPARENT LATCHES
PI74FCT162373T
PI74FCT162H373T
Fast CMOS 16-Bit
Transparent Latches
ProductFeatures:
CommonFeatures:
Product Description:
Pericom Semiconductor’s PI74FCT series of logic circuits are pro-
duced in the Company’s advanced 0.6 micron CMOS technology,
achieving industry leading speed grades.
• PI74FCT16373T,PI74FCT162373T,andPI74FCT162H373Tare
high-speed,
low power devices with high current drive.
• Vcc=5V±10%
• Hysteresis on all inputs
• Packagesavailable:
–48-pin240milwideplasticTSSOP(A)
–48-pin300milwideplasticSSOP(V)
PI74FCT16373TFeatures:
• High output drive: IOH = –32 mA; IOL = 64 mA
• Power off disable outputs permit "live insertion"
ThePI74FCT16373T,PI74FCT162373T,andPI74FCT162H373T
are 16-bit transparent latches designed with 3-state outputs and are
intended for bus oriented applications. The Output Enable and
Latch Enable controls are organized to operate as two 8-bit latches
orone16-bitlatch. WhenLatchEnable(LE)isHIGH,theflip-flops
appear transparent to the data. The data that meets the set-up time
when LE is LOW is latched. When OE is HIGH, the bus output is
in the high impedance state.
• Typical VOLP (Output Ground Bounce) < 1.0V
atVCC =5V,TA =25°C
PI74FCT162373TFeatures:
The PI74FCT16373T output buffers are designed with a Power-
Off disable allowing “live insertion” of boards when used as
backplane drivers.
• Balanced output drivers: ±24 mA
• Reduced system switching noise
• Typical VOLP (Output Ground Bounce) < 0.6V
atVCC =5V,TA =25°C
The PI74FCT162373T has ±24 mA balanced output drivers. It is
designed with current limiting resistors at its outputs to control the
output edge rate resulting in lower ground bounce and undershoot.
This eliminates the need for external terminating resistors for most
interface applications.
PI74FCT162H373TFeatures:
• Bus Hold retains last active bus state during 3-state
• Eliminates the need for external pull-up resistors
The PI74FCT162H373T has “Bus Hold” which retains the input’s
last state whenever the input goes to high-impedance preventing
“floating”inputsandeliminatingtheneedforpull-up/downresistors.
Logic Block Diagram
1OE
1LE
2OE
2LE
1D0
2D0
D
C
D
C
1O0
2O0
TO 7 OTHER CHANNELS
TO 7 OTHER CHANNELS
PS2033A 03/11/96
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