Datasheet > PI6LC48S04

PI6LC48S04

更新时间： 2024-12-02 14:55:51

品牌	Logo	应用领域
美台 - DIODES		/
页数	文件大小	规格书
11页	1071K
描述
HiFlex? Serial Interface Clock

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PI6LC48S04 数据手册

PI6LC48S04

HiFlex Serial Interface Clock

Features

Description

ꢀÎSelectable 250MHz, 156.25MHz, 125MHz or 100MHz output

e PI6LC48S04 is a 4-output clock synthesizer designed for se-

rial reference clock applications. e device generates four cop-

ies of a selectable 250MHz, 156.25MHz, 125MHz or 100MHz

clock signal with 0.34ps phase jitter performance. e four

outputs are organized in two banks of two LVDS and two low

power HCSL ouputs.e device supports 3.3V and 2.5V voltage

supplies and is packaged in a small 32-lead TQFN package.

clock synthesized from a 25MHz fundamental mode crystal

ꢀÎFour diﬀerential clock outputs (two LVDS and two low power

HCSL outputs)

ꢀÎCrystal interface designed for 25MHz, parallel resonant

crystal

ꢀÎRMS phase jitter @ 156.25MHz, using a 25MHz crystal

(1MHz - 20MHz): 0.21ps (typical)

ꢀÎRMS phase jitter @ 156.25MHz, using a 25MHz crystal

Function Table

(12kHz - 20MHz): 0.32ps (typical)

ꢀÎPower supply noise rejection PSNR: -50dB (typical)

ꢀÎLVCMOS interface levels for the frequency select input

ꢀÎFull 3.3V or 2.5V supply voltage

Inputs

Output Frequency

F_SEL [1]

F_SEL [0]

with f_XTAL= 25MHz

0 (default)

156.25MHz

125MHz

100MHz

250MHz

ꢀÎLead-free (RoHS 6) packaging

ꢀÎ-40°C to 85°C ambient operating temperature

Note: F_SEL[1:0] are asynchronous controls.

Pin Configuration

Block Diagram

32 31 30 29 28 27 26 25

XTAL_IN

VSWING_CTRL

QA0+

QA0-

LVDS

GND

QA0-

OSC

: N

DDA

XTAL_OUT

PFD

LPF

QA1+

QA1-

VCO

QA0+

LVDS

HCSL

HSCL

GND

REF_CLK

nOEA

VDDOA

Pulldown

REF_CLK

REF_SEL

QA1-

QB0+

QB0-

Pulldown

QA1+

: 25

Pulldown

VDD

17 GND

BYPASS

F_SEL[0:1]

nOEA

QB1+

QB1-

10 11 12 13 14 15 16

nOEB

VSWING_CTRL

PI6LC48S04 RevA

10/12/15

15-0128

12 3 4 5 6 7...11

中文翻译

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