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PI6C3Q993-5I PDF预览

PI6C3Q993-5I

更新时间: 2024-09-30 20:12:35
品牌 Logo 应用领域
百利通 - PERICOM 光电二极管
页数 文件大小 规格书
10页 391K
描述
Clock Driver, CMOS, PDSO28,

PI6C3Q993-5I 技术参数

是否Rohs认证: 不符合生命周期:Transferred
包装说明:SSOP, SSOP28,.25Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.88JESD-30 代码:R-PDSO-G28
JESD-609代码:e0最大I(ol):0.012 A
端子数量:28最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:SSOP封装等效代码:SSOP28,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, SHRINK PITCH
电源:3.3 VProp。Delay @ Nom-Sup:0.5 ns
认证状态:Not Qualified子类别:Clock Drivers
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:GULL WING
端子节距:0.635 mm端子位置:DUAL
Base Number Matches:1

PI6C3Q993-5I 数据手册

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PI6C3Q991, PI6C3Q993  
3.3V Programmable Skew PLL Clock Driver  
SuperClock®  
Features  
Description  
• PI6C3Q99x family provides following products:  
PI6C3Q991:32-pinPLCCversion  
PI6C3Q993:28-pinQSOPversion  
• Inputs are 5V Tolerant  
• 4 pairs of programmable skew outputs  
• Low skew: 200ps same pair; 250ps all outputs  
• Selectable positive or negative edge synchronization:  
ExcellentforDSPapplications  
ThePI6C3Q99xfamilyisa3.3VPLL-basedclockdriver intendedfor  
high-performance computing and data-communication applica-  
tions. A key feature of the programmable skew is the ability of  
outputs to lead or lag the REF input signal. The PI6C3Q991 has 8  
programmable skew outputs in 4 banks of 2, while the PI6C3Q993  
has 6 programmable skew outputs and 2 zero skew outputs. Skew  
is controlled by 3-level input signals that may be hard-wired to  
appropriateHIGH-MID-LOWlevels.  
• Synchronous output enable  
WhentheGND/sOEpinisheldLOW,alloutputsaresynchronously  
enabled.However,ifGND/sOEisheldHIGH,alloutputsexcept3Q0  
• Input frequency: 3.75 MHz to 85 MHz  
• Output frequency: 15 MHz to 85MHz  
• 2x, 4x, 1/2, and 1/4 outputs  
• 3 skew grades:  
PI6C3Q99x:tSKEW0<750ps  
and3Q1aresynchronouslydisabled.Furthermore,whentheV  
CCQ  
/PE is held HIGH, all outputs are synchronized with the positive  
edge of the REF clock input. When V /PE is held LOW, all  
CCQ  
outputs are synchronized with the negative edge of REF. Both  
devices have LVTTL 12mA balanced drive outputs.  
PI6C3Q99x-5:tSKEW0<500ps  
PI6C3Q99x-2:tSKEW0<250ps  
• 3-level inputs for skew and PLL range control  
• PLL bypass for DC testing  
• Externalfeedback,internalloopfilter  
• 12mA balanced drive outputs  
• LowJitter:<200pspeak-to-peak  
• Industrial temperature range  
• Packaging(Pb-freeandGreenavailable):  
—32-pinPLCC  
—28-pinQSOP  
PinConfigurations  
PI6C3Q991  
PI6C3Q993  
1
REF  
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
GND  
TEST  
2F1  
2
V
CCQ  
FS  
3
4
3
2
1
32 31 30  
29  
4
3F0  
3F1  
/PE  
2F0  
3F1  
4F0  
4F1  
/PE  
5
6
7
8
9
2F0  
GND/sOE  
1F1  
5
GND/sOE  
1F1  
28  
27  
26  
25  
24  
23  
22  
21  
6
V
CCQ  
V
7
1F0  
V
CCN  
1F0  
CCQ  
V
8
4Q1  
4Q0  
GND  
3Q1  
3Q0  
V
CCN  
V
CCN  
4Q1  
4Q0  
GND  
GND  
CCN  
9
1Q0  
1Q1  
GND  
GND  
2Q0  
2Q1  
10  
11  
12  
13  
1Q0  
1Q1  
GND  
GND  
10  
11  
12  
13  
14  
V
14 15 16 17 18 19 20  
CCN  
FB  
PS8449H  
10/27/09  
09-0003  
1

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