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PI6C2408-3WIEX PDF预览

PI6C2408-3WIEX

更新时间: 2024-11-26 13:12:19
品牌 Logo 应用领域
百利通 - PERICOM 逻辑集成电路光电二极管驱动时钟
页数 文件大小 规格书
10页 200K
描述
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PI6C2408-3WIEX 数据手册

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PI6C2408  
Zero-Delay Clock Buffer  
Features  
Maximumratedfrequency:140MHz  
Lowcycle-to-cyclejitter  
Input to output delay, less than 150ps  
External feedback pin allows outputs to be synchronized  
to the clock input  
5V tolerant input*  
Operatesat3.3VVDD  
Test mode allows bypass of the PLL for system testing  
purposes (e.g., IBIS measurements)  
Description  
The PI6C2408 is a PLL-based, zero-delay buffer, with the ability  
to distribute eight outputs of up to 140 MHz at 3.3 V. Two banks of  
four outputs exist, and, depending on product option ordered, can  
supply either reference frequency, prescaled half frequency, or  
multiplied2xor4xinputclockfrequencies. ThePI6C2408familyhas  
a power-sparing feature: when input SEL2 is 0, the component will  
3-state one or both banks of outputs depending on the state of input  
SEL1. A PLL bypass test mode also exists. This product line is  
available in high-drive and industrial environment versions.  
An external feedback pin is used to synchronize the outputs to the  
input; the relationship between loading of this signal and the other  
outputs determines the input-output delay.  
The PI6C2408 is characterized for both commercial and industrial  
operation.  
Clock frequency multipliers ½x to 4x dependent on option  
Packaging(Pb-freeandGreenavailable):  
-16-pin,150-milSOIC (W)  
-16-pin173-milTSSOP (L)  
* FB_IN and CLKIN must reference the same voltage thresh-  
olds for the PLL to deliver zero delay skewing  
BlockDiagram  
PinConfiguration  
FB_IN  
CLKIN  
÷2  
PLL  
OUTA1  
OUTA2  
OUTA3  
OUTA4  
MUX  
CLKIN  
OUTA1  
OUTA2  
16  
15 OUTA4  
1
2
3
4
5
6
7
8
FB_IN  
Option (-3, -4)  
14  
13  
12  
11  
10  
9
OUTA3  
SEL1  
SEL2  
Decode  
Logic  
16-Pin  
W,L  
V
V
GND  
DD  
DD  
GND  
OUTB1  
OUTB2  
SEL2  
÷2  
OUTB4  
OUTB3  
SEL1  
OUTB1  
OUTB2  
OUTB3  
OUTB4  
Option (-2, -3)  
PI6C2408 (-1, -1H, -2, -3, -4)  
FB_IN  
PLL  
OUTA1  
OUTA2  
OUTA3  
OUTA4  
MUX  
CLKIN  
SEL2  
SEL1  
Decode  
Logic  
÷2  
MUX  
PI6C2408-6  
OUTB1  
OUTB2  
OUTB3  
OUTB4  
PS8589E  
09/15/04  
1

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