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PI6C2309-1WIX PDF预览

PI6C2309-1WIX

更新时间： 2024-11-26 14:44:11
品牌 Logo 应用领域
百利通 - PERICOM 驱动光电二极管逻辑集成电路
页数 文件大小 规格书
9页 576K
描述
PLL Based Clock Driver, 6C Series, 9 True Output(s), 0 Inverted Output(s), PDSO16, 0.150 INCH, SOIC-16

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中文翻译

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PI6C2309-1WIX 技术参数

生命周期：Obsolete零件包装代码：SOIC
包装说明：SOP,针数：16
Reach Compliance Code：unknownECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：5.84
系列：6C输入调节：MUX
JESD-30 代码：R-PDSO-G16JESD-609代码：e0
长度：9.9 mm逻辑集成电路类型：PLL BASED CLOCK DRIVER
功能数量：1反相输出次数：
端子数量：16实输出次数：9
最高工作温度：85 °C最低工作温度：-40 °C
输出特性：3-STATE封装主体材料：PLASTIC/EPOXY
封装代码：SOP封装形状：RECTANGULAR
封装形式：SMALL OUTLINE认证状态：Not Qualified
Same Edge Skew-Max（tskwd）：0.2 ns座面最大高度：1.75 mm
最大供电电压 (Vsup)：3.6 V最小供电电压 (Vsup)：3 V
标称供电电压 (Vsup)：3.3 V表面贴装：YES
温度等级：INDUSTRIAL端子面层：TIN LEAD
端子形式：GULL WING端子节距：1.27 mm
端子位置：DUAL宽度：3.9 mm
最小 fmax：133 MHzBase Number Matches：1

PI6C2309-1WIX 数据手册

 浏览型号PI6C2309-1WIX的Datasheet PDF文件第2页浏览型号PI6C2309-1WIX的Datasheet PDF文件第3页浏览型号PI6C2309-1WIX的Datasheet PDF文件第4页浏览型号PI6C2309-1WIX的Datasheet PDF文件第5页浏览型号PI6C2309-1WIX的Datasheet PDF文件第6页浏览型号PI6C2309-1WIX的Datasheet PDF文件第7页 
PI6C2305/PI6C2309  
Zero-Delay Clock Buffer  
ProductFeatures  
FunctionalDescription  
• Maximumratedfrequency:133MHz  
• Lowcycle-to-cyclejitter  
The PI6C230x is a PLL based, zero-delay buffer, with the ability  
todistributefiveoutputsonPI6C2305,nineoutputsonPI6C2309of  
up to 133MHz at 3.3V. All the outputs are distributed from a single  
clockinputCLKINandoutputCLK0performszerodelaybyconnect-  
ing a feedback to PLL.  
• Input to output delay, less than 200ps  
• Internal feedback allows outputs to be synchronized  
to the clock input  
PI6C2309 has two banks of four outputs that can be controlled by  
theselectioninputs,SEL1&SEL2.Italsohasapowersparingfeature:  
when input SEL1 is 0 and SEL2 is 1, PLL is turned off and all  
outputs are referenced from CLKIN. PI6C2305 is an 8-pin version  
of PI6C2309 without selection inputs. PI6C230X is available in  
high drive and industrial environment versions.  
• 5V tolerant input*  
• Operatesat3.3VVDD  
• Space-saving Packages:  
150-milSOIC (W)  
173-milTSSOP (L)  
* FB_IN and CLKIN must reference the same voltage thresh-  
olds for the PLL to deliver zero delay skewing  
An internal feedback on OUT0 is used to synchronize the outputs  
to the input; the relationship between loading of this signal  
and the outputs determines the input-output delay.  
PI6C230X are characterized for both commercial and industrial  
operation  
Notice: This device is subject to import restriction. Please refer  
to the Import Restriction Notice under the Ordering Information  
section.  
BlockDiagram:PI6C2309  
PinConfigurationPI6C2309  
OUT0  
PLL  
OUTA1  
OUTA2  
OUTA3  
OUTA4  
MUX  
CLKIN  
CLKIN  
OUTA1  
OUTA2  
16  
15 OUTA4  
1
2
3
4
5
6
7
8
OUT0  
SEL1  
SEL2  
Decode  
Logic  
14  
13  
12  
11  
10  
9
OUTA3  
16-Pin  
W,L  
V
V
GND  
DD  
DD  
GND  
OUTB1  
OUTB2  
SEL2  
OUTB1  
OUTB2  
OUTB3  
OUTB4  
OUTB4  
OUTB3  
SEL1  
PI6C2309 (-1, -1H)  
BlockDiagram:PI6C2305  
PinConfiguration:PI6C2305  
1
8
7
6
5
CLKIN  
CLK0  
CLK4  
OUT0  
OUT1  
OUT2  
OUT3  
OUT4  
8-Pin  
W,L  
2
CLK2  
PLL  
CLKIN  
3
4
CLK1  
GND  
V
DD  
CLK3  
PI6C2305(–1, –1H)  
PS8478B  
10/30/01  
1
1234567...9

中文翻译

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