PI6C2308A-3

更新时间： 2024-11-25 22:44:27

品牌	Logo	应用领域
百利通 - PERICOM		/
页数	文件大小	规格书
10页	388K
描述
3.3V Zero-Delay Buffer

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中文翻译

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PI6C2308A-3 数据手册

PI6C2308A

3.3V Zero-Delay Buffer

Product Features

FunctionalDescription

• 10 MHz to 140 MHz operating range

• Zero input-output propagation delay, adjustable by

capacitive load on FBK input

• Multipleconfigurations, seeAvailablePI6C2308A

Configurations table

Providingtwobanksof fouroutputs,thePI6C2308Aisa 3.3Vzero-

delay buffer designed to distribute clock signals in applications

includingPC,workstation,datacom,telecom,andhigh-performance

systems. Each bank of four outputs can be controlled by the select

inputs as shown in the Select Input Decoding Table.

The PI6C2308A provides 8 copies of a clock signal that has 150ps

phase error compared to a reference clock. The skew between the

output clock signals for PI6C2308Ais less than 200ps. When there

arenorisingedgesontheREFinput,thePI6C2308Aentersapower

downstate.Inthismode,thePLLisoffandalloutputsareHi-Z.This

resultsinlessthan12µAofcurrentdraw.TheSelectInputDecoding

table shows additional examples when the PLL shuts down. The

PI6C2308A configuration table shows all available devices.

• Input to output delay, less than 150ps

• Multiple low skew outputs

- Output-output skew less than 200ps

- Device-device skew less than 500ps

- Two banks of four outputs, Hi-Z by two select inputs

• Low Jitter, less than 200ps

• 3.3Voperation

The base part, PI6C2308A-1, provides output clocks in sync with

areferenceclock. Withfasterriseandfalltimes,thePI6C2308A-1H

isthehigh-driveversionofthePI6C2308A-1.Dependingonwhich

output drives the feedback pin, PI6C2308A-2 provides 2X and 1X

clocksignalsoneachoutputbank.ThePI6C2308A-3allowstheuser

to obtain 4X and 2X frequencies on the outputs. The PI6C2308A-4

provides 2X clock signals on all outputs. PI6C2308A (-1, -2, -3, -4)

allowsbankBtobeHi-Zwhenalloutputclocksarenotrequired.The

PI6C2308A-6allowsbankBtoswitchfromReferenceclocktohalf

ofthefrequencyofReferenceclockusingthecontrolinputsS1and

S2 if Bank A is connected to feedback FBK. In addition, using the

controlinputsS1andS2,thePI6C2308A-6allowsbankAtoswitch

fromReferenceclockto2XthefrequencyofReferenceclockifBank

B is connected to feedback FBK. For testing purposes, the select

inputs connect the input clock directly to outputs.

• Availableinindustrial&commercialtemperatures

• Packages:

-Space-saving16-pin,150-milSOIC(W)

-16-pinTSSOP(L)

BlockDiagrams

÷2

FBK

CLKA1

PLL

REF

MUX

CLKA2

CLKA3

CLKA4

Extra Divider (-3, -4)

Select Input

Decoding

÷2

CLKB1

CLKB2

CLKB3

CLKB4

Extra Divider (-2,-3)

PI6C2308A (-1, -1H, -2, -3, -4)

PinConfigurationPI6C2308A(-1,-1H,-2,-3,-4,-6)

FBK

CLKA1

PLL

REF

MUX

CLKA2

CLKA3

CLKA4

REF

CLKA1

CLKA2

FBK

CLKA4

CLKA3

Select Input

Decoding

16-Pin

W,L

÷2

MUX

GND

CLKB1

CLKB2

CLKB4

CLKB3

CLKB1

CLKB2

CLKB3

CLKB4

PI6C2308A-6

PS8385B

08/03/00

12 3 4 5 6 7...10

中文翻译

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与PI6C2308A-3相关器件

型号	品牌	获取价格	描述	数据表
PI6C2308A3L	PERICOM	获取价格	3.3V Zero-Delay Buffer
PI6C2308A-3L	ETC	获取价格	Eight Distributed-Output Clock Driver
PI6C2308A-3LI	PERICOM	获取价格	3.3V Zero-Delay Buffer
PI6C2308A-3LIX	PERICOM	获取价格	PLL Based Clock Driver, 6C Series, 8 True Output(s), 0 Inverted Output(s), PDSO16, TSSOP-1
PI6C2308A-3LX	PERICOM	获取价格	暂无描述
PI6C2308A-3W	PERICOM	获取价格	3.3V Zero-Delay Buffer
PI6C2308A-3WI	PERICOM	获取价格	3.3V Zero-Delay Buffer
PI6C2308A-3WIX	PERICOM	获取价格	PLL Based Clock Driver, 6C Series, 8 True Output(s), 0 Inverted Output(s), PDSO16, 0.150 I
PI6C2308A-4	PERICOM	获取价格	3.3V Zero-Delay Buffer
PI6C2308A4L	PERICOM	获取价格	3.3V Zero-Delay Buffer

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