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PI6C2308A-1HLIX

更新时间： 2024-11-26 13:00:59
品牌 Logo 应用领域
百利通 - PERICOM /
页数 文件大小 规格书
10页 388K
描述
PLL Based Clock Driver, 6C Series, 8 True Output(s), 0 Inverted Output(s), PDSO16, TSSOP-16

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PI6C2308A-1HLIX 技术参数

生命周期：Obsolete零件包装代码：TSSOP
包装说明：TSSOP-16针数：16
Reach Compliance Code：unknownECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：5.84
Is Samacsys：N系列：6C
输入调节：MUXJESD-30 代码：R-PDSO-G16
JESD-609代码：e0长度：5 mm
逻辑集成电路类型：PLL BASED CLOCK DRIVER功能数量：1
反相输出次数：端子数量：16
实输出次数：8最高工作温度：85 °C
最低工作温度：-40 °C输出特性：3-STATE
封装主体材料：PLASTIC/EPOXY封装代码：TSSOP
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
认证状态：Not QualifiedSame Edge Skew-Max（tskwd）：0.4 ns
座面最大高度：1.2 mm最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：3 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES温度等级：INDUSTRIAL
端子面层：TIN LEAD端子形式：GULL WING
端子节距：0.65 mm端子位置：DUAL
宽度：4.4 mm最小 fmax：140 MHz
Base Number Matches：1

PI6C2308A-1HLIX 数据手册

 浏览型号PI6C2308A-1HLIX的Datasheet PDF文件第2页浏览型号PI6C2308A-1HLIX的Datasheet PDF文件第3页浏览型号PI6C2308A-1HLIX的Datasheet PDF文件第4页浏览型号PI6C2308A-1HLIX的Datasheet PDF文件第5页浏览型号PI6C2308A-1HLIX的Datasheet PDF文件第6页浏览型号PI6C2308A-1HLIX的Datasheet PDF文件第7页 
PI6C2308A  
3.3V Zero-Delay Buffer  
Product Features  
FunctionalDescription  
• 10 MHz to 140 MHz operating range  
• Zero input-output propagation delay, adjustable by  
capacitive load on FBK input  
• Multipleconfigurations, see“AvailablePI6C2308A  
Configurations” table  
Providingtwobanksof fouroutputs,thePI6C2308Aisa 3.3Vzero-  
delay buffer designed to distribute clock signals in applications  
includingPC,workstation,datacom,telecom,andhigh-performance  
systems. Each bank of four outputs can be controlled by the select  
inputs as shown in the Select Input Decoding Table.  
The PI6C2308A provides 8 copies of a clock signal that has 150ps  
phase error compared to a reference clock. The skew between the  
output clock signals for PI6C2308Ais less than 200ps. When there  
arenorisingedgesontheREFinput,thePI6C2308Aentersapower  
downstate.Inthismode,thePLLisoffandalloutputsareHi-Z.This  
resultsinlessthan12µAofcurrentdraw.TheSelectInputDecoding  
table shows additional examples when the PLL shuts down. The  
PI6C2308A configuration table shows all available devices.  
• Input to output delay, less than 150ps  
• Multiple low skew outputs  
- Output-output skew less than 200ps  
- Device-device skew less than 500ps  
- Two banks of four outputs, Hi-Z by two select inputs  
• Low Jitter, less than 200ps  
• 3.3Voperation  
The base part, PI6C2308A-1, provides output clocks in sync with  
areferenceclock. Withfasterriseandfalltimes,thePI6C2308A-1H  
isthehigh-driveversionofthePI6C2308A-1.Dependingonwhich  
output drives the feedback pin, PI6C2308A-2 provides 2X and 1X  
clocksignalsoneachoutputbank.ThePI6C2308A-3allowstheuser  
to obtain 4X and 2X frequencies on the outputs. The PI6C2308A-4  
provides 2X clock signals on all outputs. PI6C2308A (-1, -2, -3, -4)  
allowsbankBtobeHi-Zwhenalloutputclocksarenotrequired.The  
PI6C2308A-6allowsbankBtoswitchfromReferenceclocktohalf  
ofthefrequencyofReferenceclockusingthecontrolinputsS1and  
S2 if Bank A is connected to feedback FBK. In addition, using the  
controlinputsS1andS2,thePI6C2308A-6allowsbankAtoswitch  
fromReferenceclockto2XthefrequencyofReferenceclockifBank  
B is connected to feedback FBK. For testing purposes, the select  
inputs connect the input clock directly to outputs.  
• Availableinindustrial&commercialtemperatures  
• Packages:  
-Space-saving16-pin,150-milSOIC(W)  
-16-pinTSSOP(L)  
BlockDiagrams  
÷2  
FBK  
CLKA1  
PLL  
REF  
MUX  
CLKA2  
CLKA3  
CLKA4  
Extra Divider (-3, -4)  
S2  
S1  
Select Input  
Decoding  
÷2  
CLKB1  
CLKB2  
CLKB3  
CLKB4  
Extra Divider (-2,-3)  
PI6C2308A (-1, -1H, -2, -3, -4)  
PinConfigurationPI6C2308A(-1,-1H,-2,-3,-4,-6)  
FBK  
CLKA1  
PLL  
REF  
MUX  
CLKA2  
CLKA3  
CLKA4  
16  
15  
14  
13  
12  
11  
10  
9
REF  
CLKA1  
CLKA2  
1
2
3
4
5
6
7
8
FBK  
CLKA4  
CLKA3  
S2  
S1  
Select Input  
Decoding  
16-Pin  
W,L  
V
V
DD  
DD  
÷2  
MUX  
GND  
GND  
CLKB1  
CLKB2  
S2  
CLKB4  
CLKB3  
S1  
CLKB1  
CLKB2  
CLKB3  
CLKB4  
PI6C2308A-6  
PS8385B  
08/03/00  
1
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