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PI6C2308-4WIX PDF预览

PI6C2308-4WIX

更新时间: 2024-11-26 21:09:11
品牌 Logo 应用领域
百利通 - PERICOM 驱动光电二极管逻辑集成电路
页数 文件大小 规格书
9页 442K
描述
PLL Based Clock Driver, 6C Series, 8 True Output(s), 0 Inverted Output(s), PDSO16, 0.150 INCH, SOIC-16

PI6C2308-4WIX 技术参数

生命周期:Obsolete零件包装代码:SOIC
包装说明:SOP,针数:16
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.84
系列:6C输入调节:MUX
JESD-30 代码:R-PDSO-G16JESD-609代码:e0
长度:9.9 mm逻辑集成电路类型:PLL BASED CLOCK DRIVER
功能数量:1反相输出次数:
端子数量:16实输出次数:8
最高工作温度:85 °C最低工作温度:-40 °C
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE认证状态:Not Qualified
Same Edge Skew-Max(tskwd):0.2 ns座面最大高度:1.75 mm
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
温度等级:INDUSTRIAL端子面层:TIN LEAD
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL宽度:3.9 mm
最小 fmax:133 MHzBase Number Matches:1

PI6C2308-4WIX 数据手册

 浏览型号PI6C2308-4WIX的Datasheet PDF文件第2页浏览型号PI6C2308-4WIX的Datasheet PDF文件第3页浏览型号PI6C2308-4WIX的Datasheet PDF文件第4页浏览型号PI6C2308-4WIX的Datasheet PDF文件第5页浏览型号PI6C2308-4WIX的Datasheet PDF文件第6页浏览型号PI6C2308-4WIX的Datasheet PDF文件第7页 
PI6C2308  
Zero-Delay Clock Buffer  
ProductFeatures  
FunctionalDescription  
Maximumratedfrequency:133MHz  
Lowcycle-to-cyclejitter  
The PI6C2308 is a PLL-based, zero-delay buffer, with the ability  
to distribute eight outputs of up to 133 MHz at 3.3 V. Two banks of  
four outputs exist, and, depending on product option ordered, can  
supply either reference frequency, prescaled half frequency, or  
multiplied2xor4xinputclockfrequencies. ThePI6C2308familyhas  
a power-sparing feature: when input SEL2 is 0, the component will  
3-state one or both banks of outputs depending on the state of input  
SEL1. A PLL bypass test mode also exists. This product line is  
available in high-drive and industrial environment versions.  
Input to output delay, less than 200ps  
External feedback pin allows outputs to be synchronized  
to the clock input  
5V tolerant input*  
Operatesat3.3VVDD  
Test mode allows bypass of the PLL for system testing  
purposes (e.g., IBIS measurements)  
An external feedback pin is used to synchronize the outputs to the  
input; the relationship between loading of this signal and the other  
outputs determines the input-output delay.  
Clock frequency multipliers ½x to 4x dependent on option  
Space-saving Packages:  
16-pin,150-milSOIC (W)  
16-pin173-milTSSOP (L)  
The PI6C2308 is characterized for both commercial and industrial  
operation.  
* FB_IN and CLKIN must reference the same voltage thresh-  
olds for the PLL to deliver zero delay skewing  
Notice: This device is subject to import restriction. Please refer  
to the Import Restriction Notice under the Ordering Information  
section.  
BlockDiagram  
PinConfigurationPI6C2308  
FB_IN  
CLKIN  
÷2  
PLL  
OUTA1  
OUTA2  
OUTA3  
OUTA4  
MUX  
CLKIN  
OUTA1  
OUTA2  
16  
15 OUTA4  
1
2
3
4
5
6
7
8
FB_IN  
Option (-3, -4)  
14  
13  
12  
11  
10  
9
OUTA3  
16-Pin  
W,L  
SEL1  
SEL2  
Decode  
Logic  
V
V
GND  
DD  
DD  
GND  
OUTB1  
OUTB2  
SEL2  
÷2  
OUTB4  
OUTB3  
SEL1  
OUTB1  
OUTB2  
OUTB3  
OUTB4  
Option (-2, -3)  
PI6C2308 (-1, -1H, -2, -3, -4)  
FB_IN  
PLL  
OUTA1  
OUTA2  
OUTA3  
OUTA4  
MUX  
CLKIN  
SEL2  
SEL1  
Decode  
Logic  
÷2  
MUX  
PI6C2308-6  
OUTB1  
OUTB2  
OUTB3  
OUTB4  
PS8384D  
12/07/01  
1

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