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PI6C2308-1HLIX PDF预览

PI6C2308-1HLIX

更新时间: 2024-11-28 13:12:15
品牌 Logo 应用领域
百利通 - PERICOM /
页数 文件大小 规格书
10页 504K
描述
PLL Based Clock Driver, 6C Series, 8 True Output(s), 0 Inverted Output(s), PDSO16, 0.173 INCH, TSSOP-16

PI6C2308-1HLIX 技术参数

生命周期:Obsolete零件包装代码:TSSOP
包装说明:0.173 INCH, TSSOP-16针数:16
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.84
Is Samacsys:N系列:6C
输入调节:MUXJESD-30 代码:R-PDSO-G16
JESD-609代码:e0长度:5 mm
逻辑集成电路类型:PLL BASED CLOCK DRIVER功能数量:1
反相输出次数:端子数量:16
实输出次数:8最高工作温度:85 °C
最低工作温度:-40 °C输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
认证状态:Not QualifiedSame Edge Skew-Max(tskwd):0.2 ns
座面最大高度:1.2 mm最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):3 V标称供电电压 (Vsup):3.3 V
表面贴装:YES温度等级:INDUSTRIAL
端子面层:TIN LEAD端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
宽度:4.4 mm最小 fmax:133 MHz
Base Number Matches:1

PI6C2308-1HLIX 数据手册

 浏览型号PI6C2308-1HLIX的Datasheet PDF文件第2页浏览型号PI6C2308-1HLIX的Datasheet PDF文件第3页浏览型号PI6C2308-1HLIX的Datasheet PDF文件第4页浏览型号PI6C2308-1HLIX的Datasheet PDF文件第5页浏览型号PI6C2308-1HLIX的Datasheet PDF文件第6页浏览型号PI6C2308-1HLIX的Datasheet PDF文件第7页 
PI6C2308  
3.3V Zero-Delay Buffer  
ProductFeatures  
FunctionalDescription  
10 MHz to 134 MHz operating range  
Zero input-output propagation delay, adjustable by external  
capacitive load on FBK input  
Multipleconfigurations,see“AvailablePI6C2308  
Configurations” table  
Providing two banks of four outputs, the PI6C2308 is a 3.3V zero-  
delay buffer designed to distribute clock signals in applications  
includingPC,workstation,datacom,telecom,andhigh-performance  
systems. Each bank of four outputs can be controlled by the select  
inputs as shown in the Select Input Decoding Table.  
The PI6C2308 provides 8 copies of a clock signal that has 200ps  
phase error compared to a reference clock. The skew between the  
output clock signals for PI6C2308 is less than 200ps. When there  
are no rising edges on the REF input, the PI6C2308 enters a power  
down state. In this mode, the PLL is off and all outputs are Hi-Z.  
This results in less than 12µA of current draw. The Select Input  
Decoding Table shows additional examples when the PLL shuts  
down.ThePI6C2308configurationtableshowsall availabledevices.  
Input to output delay, less than 200ps  
Multiple low skew outputs  
- Output-output skew less than 200ps  
- Device-device skew less than 600ps  
- Two banks of four outputs, Hi-Z by two select inputs  
Low Jitter, less than 200ps  
3.3Voperation  
The base part, PI6C2308-1, provides output clocks in sync with a  
reference clock. With faster rise and fall times, the PI6C2308-1H  
is the high drive version of the PI6C2308-1. Depending on which  
output drives the feedback pin, PI6C2308-2 provides 2X and 1X  
clocksignalsoneachoutputbank. ThePI6C2308-3allowstheuser  
to obtain 4X and 2X frequencies on the outputs. The PI6C2308-4  
provides2Xclocksignalsonalloutputs.PI6C2308(-1,-2,-3,-4)allows  
bank B to be Hi-Z when all output clocks are not required.The  
PI6C2308-6 allows bank B to switch from Reference clock to half  
ofthefrequencyofReferenceclockusingthecontrolinputsS1and  
S2 if Bank A is connected to feedback FBK. In addition, using the  
control inputs S1 and S2, the PI6C2308-6 allows bank A to switch  
from Reference clock to 2X the frequency of Reference clock if  
Bank B is connected to feedback FBK. For testing purposes, the  
select inputs connect the input clock directly to outputs.  
Space-saving Packages:  
16-pin, 150-mil SOIC package (W16) (-1, -1H, -2, -3, -4, -6)  
16-pinTSSOPpackage(L16)(-1,-1H)  
Available in industrial and commercial temperatures  
BlockDiagrams  
Pin Configuration PI6C2308 (–1, –1H, –2, –3, –4, –6)  
16-Pin  
W,L  
PS8384D  
06/26/01  
1

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