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PI6C2305-1HLX PDF预览

PI6C2305-1HLX

更新时间: 2024-11-25 13:12:19
品牌 Logo 应用领域
百利通 - PERICOM /
页数 文件大小 规格书
6页 177K
描述
PLL Based Clock Driver, 6C Series, 5 True Output(s), 0 Inverted Output(s), PDSO8, 0.173 INCH, TSSOP-8

PI6C2305-1HLX 技术参数

是否无铅:含铅是否Rohs认证:不符合
生命周期:Obsolete零件包装代码:SOIC
包装说明:TSSOP,针数:8
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.89
Is Samacsys:N系列:6C
输入调节:STANDARDJESD-30 代码:R-PDSO-G8
JESD-609代码:e0长度:4.4 mm
逻辑集成电路类型:PLL BASED CLOCK DRIVER湿度敏感等级:1
功能数量:1反相输出次数:
端子数量:8实输出次数:5
最高工作温度:70 °C最低工作温度:
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度(摄氏度):240
认证状态:Not QualifiedSame Edge Skew-Max(tskwd):0.2 ns
座面最大高度:1.2 mm最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):3 V标称供电电压 (Vsup):3.3 V
表面贴装:YES温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30宽度:3 mm
最小 fmax:133 MHzBase Number Matches:1

PI6C2305-1HLX 数据手册

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PI6C2305-1  
3.3V Zero-Delay Buffer  
Features  
Description  
Zero-input-output propagation delay  
350ps phase error  
Providingfivelow-skewclocks,thePI6C2305-1isa 3.3Vzero-delay  
bufferdesignedtodistributeclocksignalsinapplicationsincluding  
PC,workstation,datacom,telecom,andhigh-performancesystems.  
Multiple low-skew outputs  
– Output-output skew less than 250ps  
– Device-device skew less than 700ps  
10 MHz to 100 MHz operating range  
LowJitter<200ps  
The PI6C2305-1 provides 5 copies of clocks that have less than  
350ps propagation delay compared to a reference clock. The skew  
among the output clock signals for PI6C2305-1 is less than 250ps.  
When there are no rising edges on the REF input, the PI6C2305-1  
entersapower-downstate.Inthismode,thePLLisoffandalloutputs  
are three-stated. This results in less than 50µA of current draw.  
Featuringfasterriseandfalltimes,thePI6C2305-1Histhehigh-drive  
versionofthePI6C2305-1.  
Highdriveoption(PI6C2305-1H)  
3.3Voperation  
CommercialOperation: 0°Cto+70°C  
IndustrialOperation: –40°Cto+85°C  
Package:Space-saving8-pin,150-milSOICpackage(W)  
BlockDiagram  
PinConfiguration  
8-Pin  
W
Pin Description  
Pin  
1
Signal  
Description  
Input reference frequency, 5V Tolerant input  
Buffered Clock output  
Buffered Clock output  
Ground  
(1)  
REF  
(2)  
2
CLK2  
CLK1  
(2)  
3
4
GND  
(2)  
5
CLK3  
Buffered Clock output  
3.3V Supply  
6
V
DD  
Notes:  
1. Weakpull-down.  
2. Weak pull-down  
(2)  
7
CLK4  
CLK0  
Buffered Clock output  
(2)  
8
Buffered Clock output, internal feedback on this pin  
on all outputs.  
PS9477A  
06/06/00  
1

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