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PI6C2302 PDF预览

PI6C2302

更新时间: 2024-11-24 22:44:27
品牌 Logo 应用领域
百利通 - PERICOM 时钟驱动器
页数 文件大小 规格书
4页 280K
描述
Phase-Locked Loop Clock Driver

PI6C2302 数据手册

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PI6C2302  
Phase-Locked Loop Clock Driver  
ProductFeatures  
ProductDescription  
The PI6C2302 features a low-skew, low-jitter, phase-locked loop  
(PLL)clockdriver. ByconnectingthefeedbackCLK_OUToutput  
to the feedback FB_IN input, the propagation delay from the  
CLK_INinputtoanyclockoutputwillbenearlyzero.ThePI6C2302  
provides 2X CLK_IN on CLK_OUT output.  
2X CLK_INonCLK_OUT  
High-PerformancePhase-Locked-LoopClockDistribution  
for Networking, ATM, 100/134 MHz Registered DIMM  
Synchronous DRAM modules for server/workstation/  
PC applications  
Application  
Zero Input-to-Output delay  
If the system designer needs more than 16 outputs with the features  
just described, using two or more zero-delay buffers such as  
PI6C2509Q,andPI6C2510Q,islikelytobeimpractical.Thedevice-  
to-device skew introduced can significantly reduce the perfor-  
mance. Pericom recommends the use of a zero-delay buffer and an  
eighteen output non-zero-delay buffer. As shown in  
Figure1, thiscombinationproducesazero-delaybufferwithallthe  
signal characteristics of the original zero-delay buffer, but with as  
manyoutputsasthenon-zero-delaybufferpart. Forexample, when  
combined with an eighteen output non-zero delay buffer, a system  
designer can create a seventeen-output zero-delay buffer.  
Lowjitter:Cycle-to-Cyclejitter±100psmax.  
On-chip series damping resistor at clock output drivers  
for low noise and EMI reduction  
Operatesat3.3VV  
CC  
Wide range of Clock Frequencies  
Package:  
Plastic8-pinSOICPackage(W)  
ProductPinConfiguration  
LogicBlockDiagram  
1
CLK_IN  
AV  
8
7
6
5
FB_IN  
CC  
V
8-Pin  
W
2
3
4
CC  
AGND  
GND  
S
CLK_OUT  
ControlInput  
S
Output Source  
PLL  
PLL Shutdown  
1
0
N
Y
CLK_IN  
Figure1.ThisCombinationProvidesZero-DelayBetweenthe  
Reference Clocks Signal and 17 Outputs  
PS8418B  
05/21/01  
1

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