Datasheet > PI6C2301W

PI6C2301W

更新时间： 2024-11-27 23:27:39

品牌	Logo	应用领域
其他 - ETC		时钟驱动器
页数	文件大小	规格书
4页	438K
描述
Clock Driver

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中文翻译

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PI6C2301W 数据手册

PI6C2301

Phase-Locked Loop Clock Driver

Product Features

Product Description

The PI6C2301 features a low-skew, low-jitter, phase-locked loop

(PLL)clockdriver. ByconnectingthefeedbackCLK_OUToutput

to the feedback FB_IN input, the propagation delay from the

CLK_IN input to any clock output will be nearly zero.

• High-PerformancePhase-Locked-LoopClockDistributionfor

Networking, ATM, 100/134MHzRegisteredDIMMSynchro-

nous DRAM modules for server/workstation/PC applications

• Zero Input-to-Output delay

• Lowjitter:Cycle-to-Cyclejitter ±100psmax.

Application

If the system designer needs more than 16 outputs with the features

just described, using two or more zero-delay buffers such as

PI6C2509Q, and PI6C2510Q, is likely to be impractical. The

device-to-device skew introduced can significantly reduce

the performance. Pericom recommends the use of a zero-delay

buffer and an eighteen output non-zero-delay buffer . As shown in

Figure1, thiscombinationproducesazero-delaybufferwithallthe

signal characteristics of the original zero-delay buffer, but with as

manyoutputsasthenon-zero-delaybufferpart. Forexample, when

combined with an eighteen output non-zero delay buffer, a system

designer can create a seventeen-output zero-delay buffer.

• On-chip series damping resistor at clock output drivers

for low noise and EMI reduction

• Operatesat3.3VV

• Packaged in Plastic 8-pin SOIC Package (W)

• Wide range of Clock Frequencies

Notice: This device is subject to import restriction. Please refer

to the Import Restriction Notice under the Ordering Information

section.

Logic Block Diagram

Product Pin Configuration

CLK_IN

FB_IN

CLK_OUT

CLK_IN

FB_IN

PLL

8-Pin

AGND

GND

CLK_OUT

Feedback

Control Input

Output Source

PLL

PLL Shutdown

18 Output

Non-Zero

Delay

Zero Delay

Buffer

PI6C2301

CLK_OUT

CLK_IN

Buffer

Reference

Clock

Signal

Figure 1. This Combination Provides Zero-Delay Between

the Reference Clocks Signal and 17 Outputs

PS8419A

12/07/01

12 3 4

中文翻译

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与PI6C2301W相关器件

型号	品牌	获取价格	描述	数据表
PI6C2301WX	PERICOM	获取价格	PLL Based Clock Driver, 6C Series, 1 True Output(s), 0 Inverted Output(s), PDSO8, 0.150 IN
PI6C2302	PERICOM	获取价格	Phase-Locked Loop Clock Driver
PI6C2302W	PERICOM	获取价格	Phase-Locked Loop Clock Driver
PI6C2302-WI	PERICOM	获取价格	Phase-Locked Loop Clock Driver
PI6C2302-WIE	PERICOM	获取价格	暂无描述
PI6C2302-WIEX	PERICOM	获取价格	PLL Based Clock Driver, 6C Series, 1 True Output(s), 0 Inverted Output(s), PDSO8, 0.150 IN
PI6C2302-WIX	PERICOM	获取价格	PLL Based Clock Driver, 6C Series, 1 True Output(s), 0 Inverted Output(s), PDSO8, 0.150 IN
PI6C2305-1	PERICOM	获取价格	3.3V Zero-Delay Buffer
PI6C2305-1HL	PERICOM	获取价格	PLL Based Clock Driver, 6C Series, 5 True Output(s), 0 Inverted Output(s), CMOS, PDSO8, 0.
PI6C2305-1HLE	PERICOM	获取价格	PLL Based Clock Driver, 6C Series, 5 True Output(s), 0 Inverted Output(s), PDSO8, 0.173 IN