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PI6C21900ZDE PDF预览

PI6C21900ZDE

更新时间: 2024-11-26 07:05:31
品牌 Logo 应用领域
百利通 - PERICOM /
页数 文件大小 规格书
19页 551K
描述
PLL Based Clock Driver, 6C Series, 19 True Output(s), 0 Inverted Output(s), GREEN, MO-220I/VNND, TQFN-72

PI6C21900ZDE 数据手册

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PI6C21900  
PCI Express Gen II1:19 Geared Differential Buffer  
-17 and 2 Outputs  
Description  
Features  
PI6C21900isaPCIExpressGenIIcompliant,high-speed,low-noise  
PCI-Express and FBDIMM differential clock buffer designed to be  
a companion to the workstation/server clock synthesizer such as  
PI6C410B. Thedevicedistributesnineteencopiesofthedifferential  
SRC clock, such as the one sourced from PI6C410B. To adapt to  
different systems and to offer various performance platforms, the  
PI6C21900outputscanbeprogrammedtodifferentfrequency. The  
output frequency ratio can be modied to offer various derivative  
frequency from the input frequency. Most of the output pair is  
controlled by individual OE pin. Some OE# pins service multiple  
differentialoutputpairs.Theclockoutputsarecontrolledbytheinput  
selectionbits:SA_0,SA_1,SA_2throughexternalselectpinsorvia  
• Phase jitter lter for PCIe Gen II application  
• Nineteen Pairs of differential HCSL buffers  
-17 and 2 outputs  
• Low skew < 100 ps within Dif (17:0) group  
• Low phase jitter < 108 ps (PLL mode)  
• Output Enable (OE) pins for all outputs  
• Outputs tristate control via SMBus  
• Power Management Control  
• Programmable PLL Bandwidth  
• PLL or PLL Bypass (Fanout) mode  
• Gear Ratios for different input to output frequencies  
- Input: 100, 133, 166, 200, 266, 333, or 400 MHz  
- Output: 100, 133, 166, or 200 MHz  
• 3.3V Operation  
SMBus, using SCL (SMBus Clock) and SDA (SMBus Data) pins.  
• Packaging (Pb-Free and Green):  
—72-pin TQFN (ZD)  
Block Diagram  
Pinout Conguration  
OE_17_18#  
18 17 16 15 14 13 12 11 10  
9 8 7 6 5 4 3 2 1  
DIF SWITCH 18:17  
Gear  
Shift  
Logic  
Spread  
Compatible  
PLL  
2
72 SA_2/PLL/BYPASS#  
71 CLK_IN#  
70 CLK_IN  
69 OE_17_18#  
68 DIF_18#  
67 DIF_18  
SCL 19  
SDA 20  
Stop  
Logic  
OE_5# 21  
DIF_5 22  
DIF_5# 23  
OE_6# 24  
DIF_6 25  
DIF_6# 26  
VDD 27  
13  
OE(16:5)#,  
OE_01234#  
DIF (16:00)  
66 DIF_17#  
65 DIF_17  
Spread  
Compatible  
PLL  
Gear  
Shift  
Logic  
CLK_IN  
17  
Stop  
Logic  
CLK_IN#  
64 VSS  
63 VDD  
62 DIF_16#  
61 DIF_16  
60 OE_16#  
59 DIF_15#  
58 DIF_15  
57 OE_15#  
56 DIF_14#  
55 DIF_14  
VSS 28  
HIGH_RW#  
FS_A  
OE_7# 29  
DIF_7 30  
DIF_7# 31  
OE_8# 32  
DIF_8 33  
DIF_8# 34  
SA_0 35  
Control  
Logic  
SMB_A0  
SMB_A1  
SMB_A2 PLLBYP#  
SMBDAT  
SMBCLK  
17  
SA_1  
36  
37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54  
07-0152  
PS8897A  
06/22/07  
1

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