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PI6C21900SZDE PDF预览

PI6C21900SZDE

更新时间: 2024-11-25 15:47:51
品牌 Logo 应用领域
百利通 - PERICOM 驱动逻辑集成电路
页数 文件大小 规格书
19页 523K
描述
PLL Based Clock Driver, 6C Series, 19 True Output(s), 0 Inverted Output(s), GREEN, MO-220I/VNND, TQFN-72

PI6C21900SZDE 技术参数

是否Rohs认证:符合生命周期:Obsolete
零件包装代码:QFN包装说明:HVQCCN, LCC72,.39SQ,20
针数:72Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.82Is Samacsys:N
其他特性:PLL BYPASS (FANOUT) OPERATION AVAILABLE系列:6C
输入调节:STANDARDJESD-30 代码:S-XQCC-N72
JESD-609代码:e3长度:10 mm
逻辑集成电路类型:PLL BASED CLOCK DRIVER最大I(ol):0.001 A
功能数量:1反相输出次数:
端子数量:72实输出次数:19
最高工作温度:70 °C最低工作温度:
输出特性:3-STATE封装主体材料:UNSPECIFIED
封装代码:HVQCCN封装等效代码:LCC72,.39SQ,20
封装形状:SQUARE封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度(摄氏度):260电源:3.3 V
Prop。Delay @ Nom-Sup:5.5 ns认证状态:Not Qualified
Same Edge Skew-Max(tskwd):0.25 ns座面最大高度:0.84 mm
子类别:Clock Drivers最大供电电压 (Vsup):3.465 V
最小供电电压 (Vsup):3.135 V标称供电电压 (Vsup):3.3 V
表面贴装:YES温度等级:COMMERCIAL
端子面层:MATTE TIN端子形式:NO LEAD
端子节距:0.5 mm端子位置:QUAD
处于峰值回流温度下的最长时间:40宽度:10 mm
Base Number Matches:1

PI6C21900SZDE 数据手册

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PI6C21900S  
PCI Express GenII 1:19 Geared Differential  
Buffer -18 and 1 Outputs  
Description  
Features  
PI6C21900S is a PCI Express Gen-II complient, high-speed, low-  
noisePCI-ExpressandFBDIMMdifferentialclockbufferdesigned  
tobeacompaniontotheworkstation/serverclocksynthesizersuchas  
PI6C410B. Thedevicedistributesnineteencopiesofthedifferential  
SRC clock, such as the one sourced from PI6C410B. To adapt to  
different systems and to offer various performance platforms, the  
PI6C21900S outputs can be programmed to different frequency.  
Theoutputfrequency ratio can bemodiedtooffervariousderiva-  
tive frequency from the input frequency. Most of the output pair is  
controlled by individual OE pin. Some OE# pins service multiple  
differentialoutputpairs.Theclockoutputsarecontrolledbytheinput  
selectionbits:SA_0,SA_1,SA_2throughexternalselectpinsorvia  
• Phase jitter lter for PCIe GenII application  
• Nineteen Pairs of differential HCSL buffers  
-18 and 1 outputs  
• Low skew < 100ps within Dif (16:0) group  
• Low phase jitter < 108ps (PLL mode)  
• Output Enable (OE) pins for all outputs  
• Outputs tristate control via SMBus  
• Power Management Control  
• Programmable PLL Bandwidth  
• PLL or PLL Bypass (Fanout) mode  
• Gear Ratios for different input to output frequencies  
- Input: 100, 133, 166, 200, 266, 333, or 400 MHz  
- Output: 100, 133, 166 or 200 MHz  
• 3.3V Operation  
SMBus, using SCL (SMBus Clock) and SDA (SMBus Data) pins.  
• Packaging (Pb-Free and Green):  
—72-pin TQFN (ZD)  
Block Diagram  
Pinout Conguration  
OE18#  
18 17 16 15 14 13 12 11 10  
9 8 7 6 5 4 3 2 1  
DIF (18)  
Gear  
Shift  
Logic  
Spread  
Compatible  
PLL  
1
72 SA_2/PLL/BYPASS#  
71 CLK_IN#  
70 CLK_IN  
69 OE_18#  
68 DIF_18#  
67 DIF_18  
SCL 19  
SDA 20  
Stop  
Logic  
OE_5# 21  
DIF_5 22  
DIF_5# 23  
OE_6# 24  
DIF_6 25  
DIF_6# 26  
VDD 27  
OE16_17#  
13  
OE(15:5)#,  
OE_01234#  
DIF (17:0)  
66 DIF_17#  
65 DIF_17  
Spread  
Compatible  
PLL  
Gear  
Shift  
Logic  
CLK_IN  
18  
Stop  
Logic  
CLK_IN#  
64 VSS  
63 VDD  
62 DIF_16#  
61 DIF_16  
60 OE_16_17#  
59 DIF_15#  
58 DIF_15  
57 OE_15#  
56 DIF_14#  
55 DIF_14  
VSS 28  
HIGH_RW#  
FS_A_410  
OE_7# 29  
DIF_7 30  
DIF_7# 31  
OE_8# 32  
DIF_8 33  
DIF_8# 34  
SA_0 35  
Control  
Logic  
SMB_A0  
SMB_A1  
SMB_A2 PLLBYP#  
SMBDAT  
SMBCLK  
IREF  
SA_1  
36  
37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54  
07-0151  
PS8898A  
06/22/07  
1

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