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PI6C20800S_10 PDF预览

PI6C20800S_10

更新时间: 2024-11-26 01:19:35
品牌 Logo 应用领域
百利通 - PERICOM PC
页数 文件大小 规格书
10页 619K
描述
PCI Express 1:8 HCSL Clock Buffer

PI6C20800S_10 数据手册

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PI6C20800S  
PCI Express® 1:8  
HCSL Clock Buffer  
Features  
Description  
PI6C20800SꢀisꢀaꢀPCIꢀExpress®,ꢀhigh-speed,ꢀlow-noiseꢀdifferentialꢀ  
clockꢀ bufferꢀ designedꢀ toꢀ beꢀ aꢀ companionꢀ toꢀ PI6C410BSꢀ PCIꢀ  
Expressꢀ clockꢀ generatorꢀ forꢀ Intelꢀ serverꢀ chipsets.ꢀ ꢀ Theꢀ deviceꢀ  
distributestheꢀdifferentialꢀSRCꢀclockꢀfromꢀPI6C410BSꢀtoꢀeightꢀ  
differentialꢀ pairsꢀ ofꢀ clockꢀ outputsꢀ eitherꢀ withꢀ orꢀ withoutꢀ PLL.ꢀ  
TheinputSRCclockcanbedividedby2whenSRC_DIV#isꢀ  
LOW.ꢀ ꢀ Theꢀ clockꢀ outputsꢀ areꢀ controlledꢀ byꢀ inputꢀ selectionꢀ ofꢀ  
SRC_STOP#,ꢀPWRDWN#ꢀandꢀSMBus,ꢀSCLKꢀandꢀSDA.ꢀWhenꢀ  
inputꢀofꢀeitherꢀSRC_STOP#ꢀorꢀPWRDWN#ꢀisꢀLOW,ꢀtheꢀoutputꢀ  
clocksareTristated.WhenPWRDWN#isLOW,theSDAandꢀ  
SCLKꢀinputsꢀmustꢀbeꢀTristated.  
•ꢀ PhaseꢀjitterꢀfilterꢀforꢀPCIe®ꢀapplication  
•ꢀ EightꢀPairsꢀofꢀDifferentialꢀClocks  
•ꢀ Lowꢀskewꢀ<ꢀ50psꢀ(PI6C20800S),ꢀ<60psꢀ(PI6C20800SI)  
•ꢀ LowꢀCycle-to-cycleꢀjitterꢀ<ꢀ50ps  
•ꢀ OutputꢀEnableꢀforꢀallꢀoutputs  
•ꢀ OutputsꢀTristateꢀcontrolꢀviaꢀSMBus  
•ꢀ PowerꢀManagementꢀControl  
•ꢀ ProgrammableꢀPLLꢀBandwidth  
•ꢀ PLLꢀorꢀFanoutꢀoperation  
•ꢀ 3.3VꢀOperation  
•ꢀ IndustrialꢀTemperatureꢀOptionꢀ-ꢀPI6C20800SI  
•ꢀ Packagingꢀ(Pb-Freeꢀ&ꢀGreen):  
—ꢀ48-PinꢀSSOPꢀ(V)ꢀ  
ꢀ —ꢀ48-PinꢀTSSOPꢀ(A)  
Block Diagram  
Pin Configuration  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
SRC_DIV#  
VDD  
VDD_A  
VSS_A  
IREF  
LOCK  
OE_7  
1
2
VSS  
SRC  
3
OE_INV  
OE [0:7]  
SRC_STOP#  
PWRDWN#  
Output  
Control  
4
SRC#  
OE_0  
OE_3  
OUT0  
OUT0#  
VSS  
5
OUT0  
OUT0#  
OE_4  
6
OUT7  
OUT7#  
OE_INV  
VDD  
OUT6  
OUT6#  
OE_6  
7
OUT1  
OUT1#  
SCLK  
SDA  
8
SMBus  
Controller  
OUT2  
9
OUT2#  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
PLL/BYPASS#  
SRC_DIV#  
OUT3  
VDD  
OUT3#  
OUT1  
OUT1#  
OE_1  
OE_2  
OUT2  
OUT2#  
VSS  
OUT4  
SRC  
OUT4#  
OE_5  
SRC#  
OUT5  
OUT5  
OUT5#  
VSS  
OUT5#  
OUT6  
OUT6#  
DIV  
VDD  
PLL_BW#  
PLL  
OUT7  
VDD  
OUT4  
OUT4#  
PLL_BW#  
SRC_STOP#  
PWRDWN#  
VSS  
OUT7#  
OUT3  
OUT3#  
PLL/BYPASS#  
SCLK  
SDA  
LOCK  
PS8887D  
03/29/10  
10-0150  
1

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