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PI6C20400SHE PDF预览

PI6C20400SHE

更新时间: 2024-11-26 01:09:23
品牌 Logo 应用领域
百利通 - PERICOM PC
页数 文件大小 规格书
10页 465K
描述
1 4 Clock Driver for Intel PCI Express Chipsets

PI6C20400SHE 数据手册

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PI6C20400S  
1:4 Clock Driver for Intel  
PCI Express Chipsets  
Features  
Description  
• Phase jitter lter for PCIe Gen II application  
• Four Pairs of Differential Clocks  
• Low skew < 50ps  
Pericom Semiconductor's PI6C20400S is a PCI Express GenII  
compliant high-speed, low-noise differential clock buffer designed  
to be companion to PI6C410BS. The device distributes the  
differential SRC clock from PI6C410BS to four differential pairs  
of clock outputs either with or without PLL. The clock outputs  
are controlled by input selection of SRC_STOP#, PWRDWN#  
and SMBus, SCLK and SDA. When input of either SRC_STOP#  
or PWRDWN# is low, the output clocks are Tristated. When  
PWRDWN# is low, the SDA and SCLK inputs must be Tri-  
stated.  
• Low jitter < 50ps cycle-to-cycle  
• < 1 ps additive RMS phase jitter  
• Output Enable for all outputs  
• Outputs tristate control via SMBus  
• Programmable PLL Bandwidth  
• 100 MHz PLL Mode operation  
• 100 - 400 MHz Bypass Mode operation  
• 3.3V Operation  
• Packaging (Pb-free and Green):  
— 28-Pin SSOP (H28) & 28-Pin TSSOP (L28)  
Block Diagram  
Pin Conguration  
OE_INV  
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
VDD  
SRC  
SRC#  
VSS  
VDD  
OUT0  
OUT0#  
OE_0  
OUT1  
OUT1#  
VDD  
VDD_A  
VSS_A  
IREF  
OE_INV  
VDD  
OUT3  
OUT3#  
OE_3  
OUT2  
OUT2#  
VDD  
1
2
3
4
5
6
7
8
OE_0 & OE_3  
SRC_STOP#  
PWRDWN#  
Output  
Control  
OUT0  
OUT0#  
OUT1  
OUT1#  
SMBus  
Controller  
SCLK  
SDA  
OUT2  
OUT2#  
PLL/BYPASS#  
9
OUT3  
OUT3#  
SRC  
SRC#  
10  
11  
12  
13  
14  
PLL/BYPASS#  
SCLK  
PLL_BW#  
SRC_STOP#  
PWRDWN#  
DIV  
PLL_BW#  
SDA  
PLL  
07-0265  
PS8931A  
12/10/07  
1

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