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PI6C20400BHEX PDF预览

PI6C20400BHEX

更新时间: 2024-11-25 21:14:19
品牌 Logo 应用领域
美台 - DIODES 驱动光电二极管逻辑集成电路
页数 文件大小 规格书
12页 1111K
描述
PLL Based Clock Driver, 6C Series, 4 True Output(s), 0 Inverted Output(s), PDSO28, SSOP-28

PI6C20400BHEX 技术参数

是否Rohs认证: 符合生命周期:Active
包装说明:SSOP, SSOP28,.3Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.51系列:6C
输入调节:DIFFERENTIAL MUXJESD-30 代码:R-PDSO-G28
JESD-609代码:e3长度:10.2 mm
逻辑集成电路类型:PLL BASED CLOCK DRIVER最大I(ol):0.001 A
湿度敏感等级:1功能数量:1
反相输出次数:端子数量:28
实输出次数:4最高工作温度:85 °C
最低工作温度:-40 °C输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:SSOP
封装等效代码:SSOP28,.3封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, SHRINK PITCH峰值回流温度(摄氏度):260
电源:3.3 VProp。Delay @ Nom-Sup:6.5 ns
传播延迟(tpd):6.5 ns认证状态:Not Qualified
座面最大高度:2 mm子类别:Clock Drivers
最大供电电压 (Vsup):3.465 V最小供电电压 (Vsup):3.135 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
温度等级:INDUSTRIAL端子面层:MATTE TIN
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
宽度:5.3 mmBase Number Matches:1

PI6C20400BHEX 数据手册

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A product Line of  
Diodes Incorporated  
PI6C20400B  
1:4 Clock Driver for Intel PCIe® 3.0 Chipsets  
Description  
Features  
e PI6C20400B is a PCIe 3.0 compliant high-speed, low-noise  
differential clock buffer designed to be companion to PCIe 3.0  
clock generator. It is backward compatible with PCIe 1.0 and 2.0  
specification.  
ÎPhase jitter filter for PCIe 3.0 application  
ÎFour Pairs of Differential Clocks  
ÎLow skew < 50ps  
ÎLow jitter < 50ps cycle-to-cycle  
Î< 1 ps additive RMS phase jitter  
ÎOutput Enable for all outputs  
ÎOutputs tristate control via SMBus  
ÎProgrammable PLL Bandwidth  
Î100 MHz PLL Mode operation  
Î100 - 400 MHz Bypass Mode operation  
Î3.3V Operation  
e device distributes the differential SRC clock from PCIe 3.0  
clock generator to four differential pairs of clock outputs either  
with or without PLL. e clock outputs are controlled by input  
selection of SRC_STOP#, PWRDWN# and SMBus, SCLK and  
SDA. When input of either SRC_STOP# or PWRDWN# is low,  
the output clocks are Tristated. When PWRDWN# is low, the  
SDA and SCLK inputs must be Tri-stated.  
ÎPackaging (Pb-free and Green):  
-28-Pin SSOP (H28)  
-28-Pin TSSOP (L28)  
Block Diagram  
Pin Configuration  
OE_INV  
OE_0 & OE_3  
SRC_STOP#  
PWRDWN#  
Output  
Control  
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
V
SRC  
SRC#  
V
V
V
I
1
DD  
DD_A  
SS_A  
2
OUT0  
OUT0#  
3
REF  
OE_INV  
V
4
SS  
OUT1  
OUT1#  
V
DD  
5
DD  
SMBus  
Controller  
SCLK  
SDA  
OUT0  
OUT0#  
OE_0  
OUT1  
OUT1#  
OUT3  
OUT3#  
OE_3  
OUT2  
OUT2#  
6
OUT2  
OUT2#  
7
8
PLL/BYPASS#  
9
OUT3  
OUT3#  
SRC  
SRC#  
10  
11  
12  
13  
14  
V
DD  
V
DD  
PLL/BYPASS#  
SCLK  
PLL_BW#  
SRC_STOP#  
PWRDWN#  
DIV  
SDA  
PLL_BW#  
PLL  
All trademarks are property of their respective owners.  
www.diodes.com  
01/06/17  
17-0006  
1

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